Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: A semiconductor device having Cu wiring including a basic crystal structure which can reduce surface voids, and an inspecting technique for the semiconductor device. In the semiconductor device, surface voids can be reduced down to 1/10 or less of a current practical level by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 27 or less to all crystal grain boundaries of a Cu wiring to 60% or higher. Alternatively, a similar effect of surface void reduction can be obtained by specifying a barrier layer and a seed layer and setting a proportion (frequency) of occupation of a coincidence site lattice (CSL) boundary having a grain boundary Sigma value 3 to all crystal grain boundaries of a Cu wiring to 40% or higher.

Abstract: The semiconductor substrate is removed from a wafer or a chip wherein a defect has occurred and, thereby, the surface, which faces the substrate, that contacts the semiconductor substrate in an element formation portion is exposed. A cross section of the element formation portion is exposed through the irradiation of a focused ion beam. Furthermore, a microprober is adhered to the sample and, then, the sample including a foreign substance that is considered to be a cause of defects is detached from the element formation portion. The extracted sample is moved onto a supporting base for analysis and the sample is secured to the supporting base for analysis by forming a tungsten film. Thereby, detailed information can be gained concerning a defective portion that is located, in particular, in the vicinity of the surface of the semiconductor substrate from among defective portions that have occurred in the semiconductor device.

Abstract: A crystal analyzing apparatus is provided which is capable of performing three-dimensional crystal analysis. With an electron beam (B2) scanning a measured surface (S1), a detecting unit (6) detects an electron backscatter diffraction pattern from each pixel in the measured surface (S1) and a data processing block (9) analyzes the data (D1) to obtain two-dimensional distribution data (K1) about the crystal orientation of the measured surface (S1). Next, an ion beam (B1) is emitted to slice the sample (11), so as to form the next measured section (S2) at a position inward from the measured surface (S1) by a given distance (L). Two-dimensional distribution data (K2) about the crystal orientation of the measured surface (S2) is then obtained. These operation steps are repeated to sequentially obtain crystal-orientation two-dimensional distribution data (K3) to (Kn) about measured surfaces (S3) to (Sn).

Abstract: The semiconductor substrate is removed from a wafer or a chip wherein a defect has occurred and, thereby, the surface, which faces the substrate, that contacts the semiconductor substrate in an element formation portion is exposed. A cross section of the element formation portion is exposed through the irradiation of a focused ion beam. Furthermore, a microprober is adhered to the sample and, then, the sample including a foreign substance that is considered to be a cause of defects is detached from the element formation portion. The extracted sample is moved onto a supporting base for analysis and the sample is secured to the supporting base for analysis by forming a tungsten film. Thereby, detailed information can be gained concerning a defective portion that is located, in particular, in the vicinity of the surface of the semiconductor substrate from among defective portions that have occurred in the semiconductor device.

Abstract: An FIB apparatus (101) includes a probe (2) grounded through an ammeter (12). An FIB (1B) is directed to impinge upon a sample (5) while a driver (22) is controlled to gradually decrease a distance between the probe (2) and the sample (5). With the probe (2) in non-contacting relationship with the sample (5), current generated in the sample (5) by the FIB (1B) impingement flows inwardly of the sample (5). With the probe (2) in contacting relationship with the sample (5), on the other hand, the current generated in the sample (5) flows toward the probe (2). Thus, current flowing through the probe (2) increases when contact is made between the probe (2) and the sample (5). The contact between the probe (2) and the sample (5) is detected based on the amount of change in the current flowing through the probe (2) which is monitored by the ammeter (12).

Abstract: A semiconductor device is provided for convenient checking of etching states of semiconductor layers, along with a process for its preparation, wherein a test layer is formed on the same wafer where a semiconductor product is manufactured, and concurrently with and under the same formation conditions as formation a target layer forming a part of the semiconductor product, wherein the test layer is formed on a first layer and on a second layer interposed between a portion of the test layer and the first layer, with one of the first and second layers having the same etching properties as the target layer and the other of the first and second layers having different etching characteristics from the target layer.