Patents by Inventor Yukinori Ochiai
Yukinori Ochiai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7767185Abstract: An amorphous carbon rod (13) is formed in contact with a catalyst fine particle (11). The fine particle (11) is liquefied by heat treatment, and moved along the amorphous carbon rod (13). The trail of the movement is converted to a carbon nanotube.Type: GrantFiled: September 22, 2004Date of Patent: August 3, 2010Assignee: NEC CorporationInventors: Masahiko Ishida, Toshinari Ichihashi, Yukinori Ochiai, Jun-ichi Fujita
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Publication number: 20090181535Abstract: Scale down design has posed problems in an increase in the resistance value of an interconnection structure and a decrease in the resistance to electromigration and stress migration. The present invention provides an interconnection structure of a high-reliability semiconductor device which has a low resistance value even in the case of scale down design and does not produce electromigration or stress migration, and a method of manufacturing the interconnection structure. Provided are a semiconductor device which has an interconnection or a connection plug, both of which are fabricated from a mixture of a metal and carbon nanotubes, in an interconnection trench or a via hole, both of which are formed on an insulating film on a substrate on which a semiconductor device element is formed, and a method of manufacturing this semiconductor device.Type: ApplicationFiled: March 18, 2009Publication date: July 16, 2009Applicant: NEC CORPORATIONInventors: Toshitsugu SAKAMOTO, Hisao Kawaura, Toshio Baba, Fumiyuki Nihey, Yukinori Ochiai, Hiroo Hongo
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Patent number: 7518247Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.Type: GrantFiled: December 1, 2003Date of Patent: April 14, 2009Assignee: NEC CorporationInventors: Toshitsugu Sakamoto, Hisao Kawaura, Toshio Baba, Fumiyuki Nihey, Yukinori Ochiai, Hiroo Hongo
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Patent number: 7514197Abstract: The resist according to the present invention includes any one of tetrachloromethyl tetramethoxycalix [4] arene and trichloromethyl tetramethoxycalix [4] arene. The resist including such kind of components is soluble in the solvent having less effect to worsen a working environment, namely, ethyl lactate (EL), propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), ethyl propionate, n-butyl acetate and 2-heptanone. It can be developed by tetra-methyl ammonium hydroxide in addition to the above mentioned solvent. By exposing this resist by electronic ray, high resolution of 8 nm is attained, and by using this resist as a mask, various materials can be formed into a hyperfine shape. According to such kind of resist, a photosensitive resist material which has high resolution and solvable to solvents having less effect to worsen the working environment and can be developed by the solvents, a exposure method using it, and a hyperfine processing method using it are provided.Type: GrantFiled: September 4, 2003Date of Patent: April 7, 2009Assignees: NEC Corporation, Tokuyama CorporationInventors: Yukinori Ochiai, Masahiko Ishida, Junichi Fujita, Takashi Ogura, Junji Momoda, Eiji Oshima
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Publication number: 20070041886Abstract: An amorphous carbon rod (13) is formed in contact with a catalyst fine particle (11). The fine particle (11) is liquefied by heat treatment, and moved along the amorphous carbon rod (13). The trail of the movement is converted to a carbon nanotube.Type: ApplicationFiled: September 22, 2004Publication date: February 22, 2007Inventors: Masahiko Ishida, Toshinari Ichihashi, Yukinori Ochiai, Jun-ichi Fujita
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Publication number: 20060127798Abstract: The resist according to the present invention includes any one of tetrachloromethyl tetramethoxycalix [4] arene and trichloromethyl tetramethoxycalix [4] arene. The resist including such kind of components is soluble in the solvent having less effect to worsen a working environment, namely, ethyl lactate (EL), propylene glycol monomethyl ether (PGME), propylene glycol monomethyl ether acetate (PGMEA), ethyl propionate, n-butyl acetate and 2-heptanone. It can be developed by tetra-methyl ammonium hydroxide in addition to the above mentioned solvent. By exposing this resist by electronic ray, high resolution of 8 nm is attained, and by using this resist as a mask, various materials can be formed into a hyperfine shape. According to such kind of resist, a photosensitive resist material which has high resolution and solvable to solvents having less effect to worsen the working environment and can be developed by the solvents, a exposure method using it, and a hyperfine processing method using it are provided.Type: ApplicationFiled: September 4, 2003Publication date: June 15, 2006Inventors: Yukinori Ochiai, Masahiko Ishida, Junchi Fujita, Takashi Ogura, Junji Momoda, Eiji Oshima
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Publication number: 20060091557Abstract: There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.Type: ApplicationFiled: December 1, 2003Publication date: May 4, 2006Applicant: NEC CorporationInventors: Toshitsugu Sakamoto, Hisao Kawaura, Toshio Baba, Fumiyuki Nihey, Yukinori Ochiai, Hiroo Hongo
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Patent number: 6933569Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.Type: GrantFiled: September 24, 2003Date of Patent: August 23, 2005Assignee: NEC CorporationInventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
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Publication number: 20050079120Abstract: The present invention provides a process for producing a nano-graphite structure having a desired two-dimensional or three-dimensional shape, which process possesses enough potential for ultra-fine processing to allow free selection of the size, shape, and position for the construction therefor; typically a process in which the nano-graphite structure 4 is produced by such a way where a nano-structure amorphous carbon structure 2 formed on a substrate 1 in advance in the shape of a desired ultra-fine steric configuration by a beam-excited reaction is equipped with catalyst metal atoms such as iron contained therein, and when subjecting the steric structure to a low-temperature heat treatment, the structure is converted into the graphite structure 3 through a catalytic thermal reaction by means of the catalyst metal atoms involved therein, while the shape of steric configuration thereof holds.Type: ApplicationFiled: January 31, 2003Publication date: April 14, 2005Inventors: Jun-ichi Fujita, Masahiko Ishida, Fumiyuki Nihey, Yukinori Ochiai
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Publication number: 20050066882Abstract: A technique of forming an elastic DLC structure having ultra high strength by controlling an amount of focused ion beam current from 0.1 to 10 pA, and a growth rate in the range from 0.6 to 5 ?m/min. and by using hydrocarbon gas such as phenanthrene (C14H10) and pyrene (C16H10), as source gas, in an apparatus having a gas nozzle for locally maintaining a higher partial gas pressure near the substrate and a structure for confining the gas on the substrate. In this manner, the elastic DLC having the ultra high strength can be obtained of which a hardness can be controlled in a relatively broader range.Type: ApplicationFiled: June 28, 2002Publication date: March 31, 2005Inventors: Jun-ichi Fujita, Masanhiko Ishida, Yukinori Ochiai, Shinji Matsui, Takashi Kaito
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Publication number: 20040129975Abstract: A semiconductor device includes a semiconductor layer formed on an insulator, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film and extending in a first direction, source/drain regions formed in the semiconductor layer on both sides of the gate electrode, a body contact region in the semiconductor layer, a partial isolating region in which a field insulating film thicker than the gate insulating film intervenes between the semiconductor layer and an extending portion of the gate electrode, and a full isolating region in which the semiconductor layer on the insulator is removed. The full isolating region is formed to be in contact with at least a part of a side parallel to the first direction of the source/drain regions.Type: ApplicationFiled: September 24, 2003Publication date: July 8, 2004Applicant: NEC CORPORATIONInventors: Risho Koh, Shigeharu Yamagami, Jong-wook Lee, Hitoshi Wakabayashi, Yukishige Saito, Atsushi Ogura, Mitsuru Narihiro, Kohichi Arai, Hisashi Takemura, Tohru Mogami, Toyoji Yamamoto, Yukinori Ochiai
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Patent number: 5838468Abstract: The method for forming a fine pattern on a substrate disclosed includes a step of preparing a hologram having a pattern, a step of irradiating material waves (de Broglie waves) such as neutral beams, ion beams and electron beams on the hologram, and a step of imaging the pattern on the substrate with the material waves being interfered by passing through the hologram. The light source has a source that emits a beam having a coherent wave front. Since the fine patterns are formed by utilizing the interference of material waves, the minimum processing precision can be enhanced to the extent of the wavelength of the material wave.Type: GrantFiled: April 12, 1996Date of Patent: November 17, 1998Assignee: NEC CorporationInventors: Shoko Manako, Jun-ichi Fujita, Yukinori Ochiai, Shinji Matsui
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Patent number: 5736742Abstract: An in-lens type objective lens is separated into two parts along the plane perpendicular to the direction of electron or ion orbit, so that a target sample can placed between the upper part and the lower part of the lens. Coils for the two parts are serially connected so as to work as one coil. Each of the upper and lower parts of the lens is provided with a lens positioning device. If the in-lens type objective lens is of a three-piece electrostatic type, a structure is provided which enables a target sample to be placed between a first and second electrode group and the third electrode.Type: GrantFiled: October 3, 1996Date of Patent: April 7, 1998Assignee: NEC CorporationInventor: Yukinori Ochiai
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Patent number: 5626921Abstract: For forming a photoluminescence layer on a semiconductor layer, ions are irradiated to a surface portion of a semiconductor layer where a photoluminescence layer is to be formed, and then, the semiconductor layer is immersed in a solution containing hydrofluoric acid, whereby the ion-irradiated and hydrofluoric-acid-treated portion forms a photoluminescence layer.Type: GrantFiled: January 31, 1995Date of Patent: May 6, 1997Assignee: NEC CorporationInventor: Yukinori Ochiai