Patents by Inventor Yukinori Tanaka

Yukinori Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12256073
    Abstract: Provided are an image processing device capable of performing compression processing on a video captured in each video capturing mode according to a first video capturing mode and a second video capturing mode with different capturing conditions. A possible range of a quantization parameter applied in a case where the video is compressed is made different in the first video capturing mode and the second video capturing mode with different capturing conditions. The quantization parameter is determined within a first range in a case of the first video capturing mode, and the quantization parameter is determined within a second range narrower than the first range in a case of the second video capturing mode. In particular, a second upper limit value of the second range is smaller than a first upper limit value of the first range, and a second lower limit value of the second range is larger than a first lower limit value of the first range.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: March 18, 2025
    Assignee: FUJIFILM Corporation
    Inventors: Yukinori Nishiyama, Tetsu Wada, Koichi Tanaka, Tetsuya Fujikawa, Kenkichi Hayashi
  • Patent number: 12238448
    Abstract: A video creation method of creating a video is provided. The method includes setting, in an imaging region of a reference video having a first angle of view, one or more regions having a second angle of view different from the first angle of view, determining a selection region that is the region in which a subject of a recording target is included, switching the selection region, displaying an insertion video in a period between a display period of a pre-switching video which is a video of the selection region before the switching and a display period of a post-switching video which is a video of the selection region after the switching, and executing, during a display period of the insertion video, a process to change a displayed video from one of the pre-switching video or the post-switching video to the other of the pre-switching video or the post-switching video.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 25, 2025
    Assignee: FUJIFILM Corporation
    Inventors: Koichi Tanaka, Tetsu Wada, Yukinori Nishiyama, Yuya Nishio
  • Patent number: 6671012
    Abstract: To fix display panels such as LCD panels in various sizes and shapes to a common display unit body. Each of the left and right fixtures comprises fixture body, first fixing portions, and second fixing portions. Second fixing portions with through holes are formed at the position of projection portions of the display unit body. Therefore, screws are screwed into tapped holes of the projection portions through through holes, thereby fixing the fixtures to display unit body. Through holes of first fixing portions are formed at the positions of tapped holes of the display panel. Therefore, screws are screwed into tapped holes of the display panel through through holes, thereby fixing the fixtures to display panel. A plurality of fixtures are prepared for the display panel with various sizes and shapes.
    Type: Grant
    Filed: September 1, 2000
    Date of Patent: December 30, 2003
    Assignee: NEC Corporation
    Inventor: Yukinori Tanaka
  • Patent number: 5672983
    Abstract: An output buffer circuit is provided with at least two output MOS transistors of the same type. Each of the two output MOS transistors has a source terminal connected to a power supply or a ground and further has drain terminals connected to an output pad. Resistive elements connect the gate terminals of these output MOS transistors. An input terminal of an inverter is connected to an input signal line and an output terminal of the inverter is connected to the gate terminal of a first one of the at least two output MOS transistors. A charging MOS transistor of the same type as the at least two output MOS transistors has a drain terminal connected to the gate terminal of a second one of the at least two output MOS transistors. The charging MOS transistor has a source terminal connected to either the power supply or the ground and has a gate terminal connected to the input signal line.
    Type: Grant
    Filed: February 21, 1996
    Date of Patent: September 30, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Yoshinori Yamamoto, Yukinori Tanaka