Abstract: An oscillator circuit includes a first resonator, a second resonator, and a frequency adjusting unit. The second resonator has a frequency characteristic different from a frequency characteristic of the first resonator. The frequency adjusting unit is configured to change a ratio between a contribution of the first resonator and a contribution of the second resonator so as to adjust an output frequency.

Abstract: A signal transmission device drives a light-emitting element and outputs an optical signal depending on a data signal from an electronic device. The device includes an element driving portion which supplies a driving current to the light-emitting element, wherein the driving current is obtained by superimposing a modulation current on a bias current, the modulation current being dependent on the data signal indicating emitting information of the light-emitting element. A temperature compensation portion of the device controls the bias current and the modulation current depending on the temperature so that a temperature-current characteristic of the light-emitting element is reproduced based on the voltage which is dependent on the temperature and the voltage which is independent from the temperature, thereby performing current control depending on the temperature.

Abstract: An oscillator circuit includes a first resonator, a second resonator, and a frequency adjusting unit. The second resonator has a frequency characteristic different from a frequency characteristic of the first resonator. The frequency adjusting unit is configured to change a ratio between a contribution of the first resonator and a contribution of the second resonator so as to adjust an output frequency.

Abstract: A phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and has a high linearity of a phase to voltage conversion characteristic around a phase-locked point in an operation of comparing phases of random NRZ signals in a phase. By using the phase detector circuit having a circuit configuration containing a delay circuit and a combination of leapt a multiplier circuit and a subtractor circuit, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal 3 of a multiplier circuit 62 approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and thus high linearity of the phase to voltage conversion characteristic around thus phase-locked point can be realized.

Abstract: To provide a phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and have a high linearity of a phase to voltage conversion characteristic around phase-locked point in an operation of comparing phases of random NRZ signals in a phase.

Abstract: This invention provides a semiconductor device including a silicon layer, an insulating layer formed on the silicon layer, a first semiconductor device formed on the insulating film to convert light into an electric signal, and a second semiconductor device formed on the insulating film, wherein a silicon region is formed in the silicon layer to shield the second semiconductor device from light, and a through hole extending through the silicon layer except for the silicon region to input light to the first semiconductor device is formed in that portion of the silicon layer corresponding to the lower portions of the first and second semiconductor devices.

Abstract: An amplifier having an automatic threshold control circuit (ATC) and a limiting amplifier. The ATC detects and holds a top value (peak value) and bottom value of an input signal, and outputs the middle value between the top and bottom values as a reference voltage. The limiting amplifier amplifies the input signal in a linear operating region whose center is set at the reference voltage, thereby maintaining the output amplitude at a constant value. Even if the amplitude and the level of the input signals instantaneously changes by a large amount, the ATC can follow the change, so that the offset compensation and gain compensation of the amplifier can be achieved instantaneously. This makes it possible to continue producing the output of a constant amplitude with little phase deviations.

Abstract: Wideband amplifier having a differential amplifier or single-ended amplifier and having a capacitaqnce compensation circuit is disclosed. The amplifier detects the voltage variations of a signal input node or a signal output node, generates a compensation current equal in magnitude and opposite in direction to a current flowing in a parasitic capacitance such as a transistor junction capacitance, and cancels the parasitic capacitance associated with a node by supplying the compensation current in a reverse phase to the node to which the parasitic capacitance is attached. As a result, a wideband amplifier is achieved, and it can also be used as a high-speed comparator. Further, harmonic distortions causing from the voltage dependency of the parasitic capacitance can be reduced by flowing the compensation current corresponding to a voltage impressed to the junction capacitance.

Abstract: A monolithic integrated circuit device is formed on a substrate and made up of an AC negative feedback circuit for a high frequency amplifier circuit. The AC negative feedback circuit includes a semiconductor impedance element and connected to an external terminal on the substrate, and variable control means for adjusting an amount of the AC feedback of the high frequency amplifier circuit. As the semiconductor impedance element is used the junction capacitance of a diode under negative bias, diffusion capacitance between the base and emitter electrodes or between the base and collector electrodes of a transistor or a differentiated resistance of a diode.

Abstract: The analog output from a local DAC comprising an LDAC and an MDAC, in which the full scale of the LDAC is always larger than the quantized level of the MDAC, is compared with an input analog signal which is sampled and held. A digital code obtained by successive approximation in accordance with the result of the comparison is stored in a successive approximation register. A shift code for calibrating the D/A conversion in the local DAC by shifting the digital code which is previously allotted to each digital code is stored in a shift code generating circuit (ROM). The digital code from the successive approximation register is digitally shifted in accordance with the shift code by a code shift circuit such as a digital adder/subtractor to obtain an A/D conversion output. An analog to digital converter with a high accuracy and an improved conversion speed is inexpensively fabricated in the form of a one chip LSI by a usual CMOS process.

Abstract: A digital to analog converter comprising a first digital to analog converter for generating an output signal of higher order bits; a second digital to analog converter for generating a full scale output as an output signal of lower order bits which is always larger than the output value (1 LSB) corresponding to one bit of a digital input at the least significant bit of the first digital to analog converter; adding means for adding the output signal from the first digital to analog converter to the output signal from the second digital to analog converter to form an analog output signal; and a code converter for applying to the first and second digital to analog converters an input code obtained by shifting a digital input signal applied to the first and second digital to analog converters by a given value such that the relationship between the digital input signal and the analog output signal is made substantially linear.