Patents by Inventor Yukio Fuji
Yukio Fuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8129709Abstract: A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.Type: GrantFiled: November 13, 2009Date of Patent: March 6, 2012Assignee: Elpida Memory, Inc.Inventors: Akiyoshi Seko, Yukio Fuji, Natsuki Sato, Isamu Asano
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Publication number: 20110267877Abstract: A semiconductor device includes first and second phase-change memory elements (GST1 and GST2), each being programmed by a current supplied from a power supply (Vdd). A set voltage and a reset voltage supplied to a pair of complementary write bit lines (WBT and WBB) are applied respectively to gates of first and second driver transistors (WN1 and WN2) that drive the first and second phase-change memory elements via first and second write switches (WSN1 and WSN2) made conductive when a write word line is activated. The reset voltage and the set voltage are generated in a write circuit by voltage drop of predetermined voltage levels different each other from a boosted voltage (VPP) which is higher than the power supply voltage (Vdd).Type: ApplicationFiled: July 11, 2011Publication date: November 3, 2011Applicant: ELPIDA MEMORY, INC.Inventor: Yukio FUJI
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Patent number: 8050124Abstract: A semiconductor memory device includes: plural bit lines connected with plural memory cells, respectively; plural transfer lines allocated in common to the plural bit lines; sense amplifiers (SA1) and (SA2) connected to these transfer lines, respectively; and a control circuit making the sense amplifier (SA2) perform a converting operation during an amplifying operation performed by the sense amplifier (SA1). Because the plural sense amplifiers are allocated to the same bit lines, and these are operated in parallel in this way, data can be read at a high speed.Type: GrantFiled: March 21, 2008Date of Patent: November 1, 2011Assignee: Elpida Memory, Inc.Inventors: Yasuko Tonomura, Satoshi Katagiri, Yukio Fuji
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Patent number: 7983104Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.Type: GrantFiled: January 7, 2010Date of Patent: July 19, 2011Assignee: Ovonyx, Inc.Inventors: Ward Parkinson, Yukio Fuji
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Patent number: 7800940Abstract: A semiconductor memory device includes a phase-change memory and has high compatibility with DRAM interface. The memory cell array includes a memory cell that includes a phase-change element provided at the intersection of a bit line and word line. A write address and data accompanying a write request are temporarily held in a write address register and a data register respectively, and a write operation is not performed on the memory cell array in this cycle of write request. And when a next write request occurs, the held data is written to the memory cell array. At this time, two write cycles—RESET cycle and SET cycle—are provided. Then the written contents of the memory cell and the rewrite data are compared, and after only SET cells are temporarily RESET (amorphization, increasing the resistance), it is operated so as to write only SET data (crystallization, lowering the resistance).Type: GrantFiled: June 13, 2008Date of Patent: September 21, 2010Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7751227Abstract: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.Type: GrantFiled: July 10, 2009Date of Patent: July 6, 2010Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Publication number: 20100123114Abstract: A nonvolatile memory device (21) is provided with a semiconductor substrate, a plurality of active regions (3) formed on the semiconductor substrate and extending in a band, a plurality of select active elements (23) formed in the active regions (3) and having a first impurity diffusion region and a second impurity diffusion region, a plurality of first electrodes (13) electrically connected to the first impurity diffusion region, a variable resistance layer (12) electrically connected to the first electrodes (13), and a plurality of second electrodes electrically connected to the variable resistance layer (12). Among the plurality of first electrodes (13) and the plurality of second electrodes, an array direction of at least one pair of the first electrodes (13) and the second electrodes that are electrically connected to the same variable resistance layer (12), and a direction of extension of the activation regions (3) are not parallel.Type: ApplicationFiled: November 13, 2009Publication date: May 20, 2010Inventors: Akiyoshi SEKO, Yukio FUJI, Natsuki SATO, Isamu ASANO
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Publication number: 20100110782Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Inventors: Ward Parkinson, Yukio Fuji
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Patent number: 7692979Abstract: In a memory readout circuit for use in a phase-change memory device comprising phase-change elements as memory cells, a sense amplifier sets readout voltage, which is applied to a selected phase-change element selected among the phase-change elements by a column selecting switch, to voltage equal to or higher than hold voltage of the selected phase-change element but lower than transition voltage of the selected phase-change element in a readout cycle. The selected phase-change element is read out as a dynamic state in the case where the selected phase-change element is in a set state.Type: GrantFiled: November 21, 2007Date of Patent: April 6, 2010Assignee: Elpida Memory, Inc.Inventors: Yukio Fuji, Yasuko Tonomura
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Publication number: 20100067289Abstract: A semiconductor device includes first and second phase-change memory elements (GST1 and GST2), each being programmed by a current supplied from a power supply (Vdd). A set voltage and a reset voltage supplied to a pair of complementary write bit lines (WBT and WBB) are applied respectively to gates of first and second driver transistors (WN1 and WN2) that drive the first and second phase-change memory elements via first and second write switches (WSN1 and WSN2) made conductive when a write word line is activated. The reset voltage and the set voltage are generated in a write circuit by voltage drop of predetermined voltage levels different each other from a boosted voltage (VPP) which is higher than the power supply voltage (Vdd).Type: ApplicationFiled: September 10, 2009Publication date: March 18, 2010Applicant: Elpida Menory, Inc.Inventor: Yukio FUJI
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Publication number: 20100067291Abstract: When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.Type: ApplicationFiled: November 23, 2009Publication date: March 18, 2010Applicant: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7675770Abstract: A phase change memory device, comprising a phase change memory device; a semiconductor substrate; a MOS transistor disposed at each intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix form; a plurality of phase change memory elements for storing data of a plurality of bits, each formed on an upper area opposite to a diffusion layer of the MOS transistor in a phase change layer made of phase change material; a lower electrode structure for electrically connecting each of the plurality of phase change memory elements to the diffusion layer of the MOS transistor.Type: GrantFiled: February 9, 2006Date of Patent: March 9, 2010Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Yukio Fuji, Kiyoshi Nakai, Tsuyoshi Kawagoe
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Patent number: 7646633Abstract: When a phase-change element that can transition between a reset state (amorphous state) and a set state (crystalline state) is to be caused to transition to the reset state, a first pulse having a first voltage is applied to the phase-change element. The first voltage is higher than the threshold voltage in the reset state, and can cause current to flow that corresponds to an amount of generated heat required for placing the element in the reset state. When the phase-change element is to be caused to transition to the set state, a second pulse having a second voltage and the same time width as the first pulse is applied to the phase-change element. The second voltage that is higher than the threshold voltage but lower than the first voltage, and can cause only a current to flow that does not attain the necessary amount of generated heat.Type: GrantFiled: February 27, 2008Date of Patent: January 12, 2010Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7646626Abstract: An array of non-volatile memory cells arranged in logical columns and logical rows, and associated circuitry to enable reading or writing one or more memory cells on a row in parallel. In some embodiments, the array of memory cells may include a phase change material. In some embodiments, the circuitry may include a write driver, a read driver, a sense amplifier, and circuitry to isolate the memory cells from the sense amplifier with extended refresh.Type: GrantFiled: March 3, 2008Date of Patent: January 12, 2010Assignee: Ovonyx, Inc.Inventors: Ward Parkinson, Yukio Fuji
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Publication number: 20090273970Abstract: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.Type: ApplicationFiled: July 10, 2009Publication date: November 5, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Yukio FUJI
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Patent number: 7580277Abstract: Disclosed are a phase change memory with improved retention characteristic of a phase change device, and a method for refreshing the phase change memory. The fact that a memory is a DRAM interface compatible memory is exploited. There are provided dummy cells stressed in accordance with the number of times of read and write operations. Changes in the resistance value of the dummy cells are detected by comparator circuits. If the resistance value have been changed beyond a predetermined reference value (that is, changed to a low resistance), a refresh request circuit requests an internal circuit, not shown, to effect refreshing. The memory cells and the dummy cells are transitorily refreshed and correction is made for variations in the programmed resistance value of the phase change devices to assure the margin as well as to improve retention characteristic.Type: GrantFiled: September 9, 2008Date of Patent: August 25, 2009Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7554147Abstract: A memory device in which both DRAM and phase-change memory (PCRAM) are mounted is provided with a DRAM bit line, a PCRAM bit line or a PCRAM source line formed on an conductive layer shared with the DRAM bit line, and a sense amplifier connected between the DRAM bit line and the PCRAM bit line. The memory device further has a capacitive element disposed on the upper layer of the DRAM bit line, and a phase-change element disposed on the upper layer of the PCRAM bit line. The lower electrode of the capacitive element and the lower electrode of the phase-change memory element are formed on the shared conductive layer.Type: GrantFiled: March 14, 2006Date of Patent: June 30, 2009Assignee: Elpida Memory, Inc.Inventors: Isamu Asano, Tsuyoshi Kawagoe, Kiyoshi Nakai, Yukio Fuji, Kazuhiko Kajigaya
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Patent number: 7548894Abstract: An artificial neural network that can act like the real neural network according to the input history of signals input. The network includes a learning circuit that stores an input history of an input signal, an output circuit that is connected to the learning circuit, and a reset circuit that resets the input history stored in the learning circuit. The learning circuit changes a potential-change characteristic of an internal node included in the output circuit, according to the input history. The output circuit starts an output operation of data when a potential at the internal node exceeds a threshold value. The artificial neural network of this invention can operate almost in the same way as the real neural network, because it performs an output operation, such as an oscillating operation, in response to the history of the input signal.Type: GrantFiled: June 23, 2006Date of Patent: June 16, 2009Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7532508Abstract: A memory cell has a heater element which generates heat by supplying electric current, a chalcogenide layer whose phase is changed by applying heat, and two transistors for driving the heater element. Bit lines extend in a predetermined direction and electrically connect with memory cells. Word lines extend at right angles to bit lines and electrically connect with memory cells. In a first cell row, memory cells are arranged at interval 2d along the bit lines. In a second row, memory cells are arranged such that the first cell row is shifted by distance d along the bit lines. First cell rows and second cell rows are alternately arranged at an interval e along the direction of word line so as to arrange the memory cells in a checker manner.Type: GrantFiled: January 16, 2007Date of Patent: May 12, 2009Assignee: Elpida Memory, Inc.Inventor: Yukio Fuji
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Patent number: 7502252Abstract: For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.Type: GrantFiled: October 25, 2005Date of Patent: March 10, 2009Assignee: Elpida Memory Inc.Inventors: Yukio Fuji, Isamu Asano, Tsuyoshi Kawagoe, Kiyoshi Nakai