Abstract: A memory device includes a plurality of storage units in which to store data of a bank, wherein the data has a logical order prior to storage and a physical order different than the logical order within the plurality of storage units and a within-device reordering unit to reorder the data of a bank into the logical order prior to performing on-chip processing. In another embodiment, the memory device includes an external device interface connectable to an external device communicating with the memory device, an internal processing element to process data stored on the device and multiple banks of storage. Each bank includes a plurality of storage units and each storage unit has two ports, an external port connectable to the external device interface and an internal port connected to the internal processing element.

Abstract: A memory device includes at least two memory banks storing data and an internal processor. The at least two memory banks are accessible by a host processor. The internal processor receives a timeslot from the host processor and processes a portion of the data from an indicated one of the at least two banks of the memory array during the timeslot while the remaining banks are available to the host processor during the timeslot. A method of operating a memory device having banks storing data includes a host processor issuing per bank timeslots to an internal processor of a memory device, the internal processor operating on an indicated bank of the memory device during the timeslot and the host processor not accessing the indicated bank during the timeslot.

Abstract: A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A flexible multi-area memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area shared by the first and the second processors. The common area has two ports and thereby simultaneously accessible from the first and the second processors. Each capacity of the first, the second, and the common areas can be set arbitrarily.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A semiconductor memory chip in which signals are transferred as serial signal frames includes a frame decoder providing an interface between a memory core and a reception interface. The frame decoder includes a command type decoder for decoding the types of commands included in frames according to the decoded type of the commands, a memory command evaluator/generator for scheduling and preparing single commands for the core, an intermediate data buffer command evaluator/generator for scheduling and preparing control signals for an intermediate data buffer, and a system command evaluator/generator for preparing and scheduling system commands. These system commands provide timing parameters to ensure time intervals between consecutive commands within one frame or between frames and are stored in a system mode register. The operation of the frame decoder is edge-synchronized by a frame clock or a synchronization decoder clock signal which is phase-aligned to that frame clock signal.

Abstract: A semiconductor memory chip includes: a reception interface section for receiving external data, command, and address signals in form of serial signal frames; an intermediate data buffer for intermediately storing write data and, optionally, write data mask bits to be written to a memory cell array; a memory core having a bank organized memory cell array; a decoder section for decoding an address derived from a signal frame received from the reception interface section for writing/reading data in/from one or more memory banks of the memory cell array in accordance with a write/read command within one or more received signal frames; and a frame decoder provided as an interface between the reception interface section and the memory core for decoding one or more commands included in one or more frames and outputting data addresses, command, and read/write access indication signals to the memory core and to the intermediate data buffer.

Abstract: A semiconductor memory device includes semiconductor memory cells with at least one memory cell capable of acting either in a first mode, wherein it functions as a storage device for ECC information, or in a second mode, wherein it functions as either as a redundant memory cell or a as a cell storing ordinary information. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either in the first mode or in the second mode. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either in the first mode or in either of the selected second modes.

Abstract: An SDRAM memory chip device comprises a non-volatile memory controller for operating a non-volatile memory, e.g., a NAND-flash, and a FIFO memory buffer. The FIFO memory buffer serves to operate background store and load operations between a FIFO buffer array and the non-volatile memory, while a host system such as a CPU exchanges data with the SDRAM work memory. The SDRAM memory chip device, therefore, has at least two additional pins as compared with conventional SDRAM standard for generating a set of additional commands. These commands are employed by the FIFO memory buffer to manage the data transfer between the FIFO buffer and each of the non-volatile memory and the volatile SDRAM memory. Two further pins reflecting the flash memory status provide appropriate issuance of load or store signals by the host system.

Abstract: A flexible multi-area memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area shared by the first and the second processors. The common area has two ports and thereby simultaneously accessible from the first and the second processors. Each capacity of the first, the second, and the common areas can be set arbitrarily.

Abstract: A partial dual-port memory used for an electronic device such as a mobile phone includes a storage area with a given capacity. The storage area has a first area accessed only by a first processor, a second area accessed only by a second processor, and a common area having two ports, shared by the first and the second processors, and simultaneously accessible via the two ports.

Abstract: In a three-dimensional semiconductor package, a logic-circuit chip has a plurality of top electrode terminals formed on a top surface thereof, and a spacer chip is mounted on the logic-circuit chip. The spacer chip has a plurality of bottom electrode terminals formed on a bottom surface thereof, and a plurality of top electrode terminals formed on a top surface thereof and electrically connected to the respective bottom electrode terminals thereof. The mounting of the spacer chip on the logic-circuit chip is carried out such that the bottom electrode terminals of the spacer chip are bonded to the top electrode terminals of the logic-circuit chip, to thereby establish electrical connections therebetween. A memory chip is mounted on the spacer chip, and has a plurality of electrode terminals formed on a surface thereof.

Abstract: A semiconductor memory device according to the invention comprises a first memory cell region, a second memory cell region, and a sense-amplifier row region disposed between the first and second memory cell regions, wherein the sense-amplifier row region has therein a plurality of transistor rows constituting a plurality of sense-amplifiers, at least one power-supply side sense-amplifier driver transistor disposed on the side f the first memory cell region of the plurality of transistor rows, and at least one ground side sense-amplifier driver transistor disposed on the side of the second memory cell region of the plurality of transistor rows.

Abstract: There is provided a semiconductor memory including a plurality of sub-arrays each of which includes a plurality of cells arranged in a matrix, at least one word line connected to gates of cells arranged in a first direction among the cells, at least one bit line for providing a data-writing signal to one of electrodes of cells arranged in a second direction among the cells, the second direction being perpendicular to the first direction, at least one ground line for reading data out of the other of the electrodes of cells arranged in the second direction, a plurality of sense-amplifiers associated with each of the sub-arrays for providing a sense-amplifying current to the bit line, and a plurality of row buffers connected to all of the sub-arrays for retaining data of a cell selected by the word line. In accordance with the above-mentioned semiconductor memory, a plurality of row buffers for retaining data stored in cells in a sub-array selected by a word line are connected to all of the sub-arrays.

Abstract: A clock generator of the present invention comprisesa first buffer receiving a first clock, a second buffer receiving a second clock having a amplitude being different of that of the first clock, phase comparator comparing phases between an output of the first buffer and an output of the second buffer, and means for adapting a delay time of the first buffer to a delay time of the second buffer.

Abstract: In an interface for an input signal with a small amplitude and a high bit rate, the output voltage of a receiver can become more indeterminate when the input signal voltage at the receiving end of a signal transmission line becomes equal to a reference voltage V.sub.ref. In the input buffer circuit of the CMOS current mirror type, a transistor Q.sub.2 is connected in parallel with another transistor Q.sub.1, where the conductivity types of both the transistors are the same and a reference voltage V.sub.ref is applied to the gate electrode of the transistor Q.sub.1. The transistor Q.sub.2 endows the input buffer circuit with a hysteresis characteristic, and the output power N1 of the input buffer circuit is supplied to the gate electrode of the transistor Q.sub.2.

Abstract: A memory device comprises a plurality of memory cell array blocks (CAB1) each having at least one word line (WL11) and associated with a word line drive circuit (PD1a, WD1a, RD1), a block select circuit (BSa) for selectively outputting a block select signal (SL1s) corresponding to one of the memory cell array blocks, an address buffer (AB1a) for outputting word address signals (AddR1) to the memory cell array blocks wherein the word line drive circuit is associated with an address latch circuit (AL1a) which latches and continuously outputs one of the word address signals thereto, the block select signal activates the address latch circuit for latching one of the word address signals, the word line drive circuit continuously activates the word line according to an output signal (AL1aout) of the address latch circuit and deactivates the word line only when the block select signal. (Sb1s) corresponding to the memory cell array block is output from the block select circuit.

Abstract: A memory device comprises a plurality of memory cell array blocks (CAB1) each having at least one word line (WL11) and associated with a word line drive circuit (PD1a, WD1a, RD1), a block select circuit (BSa) for selectively outputting a block select signal (SL1s) corresponding to one of the memory cell array blocks, an address buffer (AB1a) for outputting word address signals (AddR1) to the memory cell array blocks wherein the word line drive circuit is associated with an address latch circuit (AL1a) which latches and continuously outputs one of the word address signals thereto, the block select signal activates the address latch circuit for latching one of the word address signals, the word line drive circuit continuously activates the word line according to an output signal (AL1aout) of the address latch circuit and deactivates the word line only when the block select signal (SL1s) corresponding to the memory cell array block is output from the block select circuit.