Patents by Inventor Yukio Hiraiwa

Yukio Hiraiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor Device and Method of Controlling the Same
    Publication number: 20120268167
    Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.
    Type: Application
    Filed: July 2, 2012
    Publication date: October 25, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Toshio Yamada, Kazuo Tanaka, Akinobu Watanabe, Shigeru Yamamoto, Yukio Hiraiwa
  • Semiconductor device and method of controlling the same
    Patent number: 8237469
    Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshio Yamada, Kazuo Tanaka, Akinobu Watanabe, Shigeru Yamamoto, Yukio Hiraiwa
  • Semiconductor Device and Method of Controlling the Same
    Publication number: 20110062990
    Abstract: A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET (“control” MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 17, 2011
    Applicant: Renesas Electronics Corporation
    Inventors: Toshio Yamada, Kazuo Tanaka, Akinobu Watanabe, Shigeru Yamamoto, Yukio Hiraiwa