Abstract: An information-processing device, information-processing method, and program capable of formulating proposed changes to social infrastructure are provided. The information-processing device has a generation unit and a formulation unit. The generation unit uses a policy function, which is a probability model for facility changes for a system having a graph structure, and generates a facility change proposal candidate. The formulation unit evaluates the reliability of the system, for each facility change proposal candidate generated by the generation unit.

Abstract: A data processing apparatus according to an embodiment includes a data acquisition unit, a setting unit, and a reinforcement learning unit. The data acquisition unit acquires graph-structured data describing a connection relation between nodes. The setting unit sets a first network representing the graph-structured data acquired by the data acquisition unit. The reinforcement learning unit derives a parameter of the first network such that a feature quantity of an output layer of an evaluation target node in the first network approaches a reward and a feature quantity of an output layer of an operation node becomes a feature quantity causing the feature quantity of the output layer of the evaluation target node to approach the reward.

Abstract: An information processing device includes a definer, a determiner, and a reinforcement learner. The definer is configured to associate a node and an edge with attributes and to define a convolution function associated with a model representing data of a graph structure representing a system structure on the basis of data regarding the graph structure. The evaluator is configured to input a state of the system into the model. The evaluator is configured to obtain, for each time step, a policy function as a probability distribution of a structural change and a state value function for reinforcement learning for a system of one or more structurally changed models which have been changed with assumable structural changes from the model for each time step. The evaluator is configured to evaluate the structural changes in the system on the basis of the policy function.

Abstract: An information processing device of embodiments includes a data acquirer and a network processor. The data acquirer is configured to acquire graph structure data that includes a plurality of real nodes and one or more real edges connecting two of the plurality of real nodes. The network processor is configured to execute processing of propagating a feature amount of a k?1th layer of each of a plurality of assumed nodes that include the plurality of real nodes and the one or more real edges at least to a feature amount of a kth layer of another assumed node in a connection relationship with each of the assumed nodes in a neural network on the basis of the graph structure data acquired by the data acquirer. k is a natural number equal to or more than 1.

Abstract: A data processing apparatus according to an embodiment includes a data acquisition unit, a setting unit, and a reinforcement learning unit. The data acquisition unit acquires graph-structured data describing a connection relation between nodes. The setting unit sets a first network representing the graph-structured data acquired by the data acquisition unit. The reinforcement learning unit derives a parameter of the first network such that a feature quantity of an output layer of an evaluation target node in the first network approaches a reward and a feature quantity of an output layer of an operation node becomes a feature quantity causing the feature quantity of the output layer of the evaluation target node to approach the reward.

Abstract: A data transmitting node and a network inter-connection node suitable for use in the home network environment. In a case of transmitting information data from a data transmitting node connected with a physical network to a receiving node connected with the physical network or another physical network, a data transmitting node transmits the control message including an IP address information of a data transmission destination, a header/channel information dependent on the physical network, and an information indicating that the information data to be transmitted according to the header/channel information is data in an upper layer of an IP layer. The information data is then transmitted to the receiving node, where the information data contains the header/channel information and data of the upper layer without IP packet encapsulation. A network inter-connection node operates similarly.

Abstract: A data transmitting node and a network inter-connection node suitable for use in the home network environment. In a case of transmitting information data from a data transmitting node connected with a physical network to a receiving node connected with the physical network or another physical network, a data transmitting node transmits the control message including an IP address information of a data transmission destination, a header/channel information dependent on the physical network, and an information indicating that the information data to be transmitted according to the header/channel information is data in an upper layer of an IP layer. The information data is then transmitted to the receiving node, where the information data contains the header/channel information and data of the upper layer without IP packet encapsulation. A network inter-connection node operates similarly.

Abstract: A data transmitting node and a network inter-connection node suitable for use in the home network environment. In a case of transmitting information data from a data transmitting node connected with a physical network to a receiving node connected with the physical network or another physical network, a data transmitting node transmits the control message including an IP address information of a data transmission destination, a header/channel information dependent on the physical network, and an information indicating that the information data to be transmitted according to the header/channel information is data in an upper layer of an IP layer. The information data is then transmitted to the receiving node, where the information data contains the header/channel information and data of the upper layer without IP packet encapsulation. A network inter-connection node operates similarly.

Abstract: A video on demand system includes one or more hybrid fiber coax access networks connecting set top units to corresponding head end units. The head end unit for an access network is connected to an asynchronous transfer mode wide area network (ATM WAN). A hierarchical system of video servers, including at least one center server and at least one local server, or cache node, are also connected to the ATM WAN. When a user wishes to select a video, a service control unit coupled to the ATM WAN generates a selection list of proposed videos for which server and network resources are available to immediately serve the user-selected video. The service control unit determines whether server and network resources are available by sending separate queries to server and network resources management control units. Alternatively, the service control unit may generate the selection list based on whether the probability of a particular video being immediately served is greater than a threshold.

Abstract: In supplying power to a plurality of electric apparatuses connected to a power line having a predetermined maximum consumable power, a power consumption of the power line is measured as a first power consumption. When a second power consumption predetermined in each of the electric apparatuses is told, a sum of the second power consumption and the first power consumption of the power line is compared with the predetermined maximum consumable power of the power line, and it is determined whether the second power consumption by the electric apparatus is permissible. A result of the determination is told to the electric apparatuses.

Abstract: In supplying power to a plurality of electric apparatuses connected to a power line having a predetermined maximum consumable power, a power consumption of the power line is measured as a first power consumption. When a second power consumption predetermined in each of the electric apparatuses is told, a sum of the second power consumption and the first power consumption of the power line is compared with the predetermined maximum consumable power of the power line, and it is determined whether the second power consumption by the electric apparatus is permissible. A result of the determination is told to the electric apparatuses.

Abstract: An information transmit system includes a first communication element having a guaranteed quality required to transmit real-time information, and a second communication element different from the first communication element. The system also includes a transmission element for transmitting stored real-time information using the first communication element and for transmitting real-time data using the second communication element, where the real-time data using the second communication element has corresponding time stamps later in time than the real-time data transmitted by the first communication element. For example, a time stamp of the real-time data may be used to transmit the data in either a normal direction (using the first communication element), or in a retrospective direction (using the second communication element).

Abstract: This invention has an object to provide a practical neural network device. The first neural network device of this invention comprises an input circuit for performing predetermined processing of external input information and generating an input signal, an arithmetic processing circuit for performing an arithmetic operation of the input signal in accordance with a plurality of control parameters and generating an output signal, and a control circuit for controlling the control parameters of the arithmetic processing circuit so that the output signal is set to satisfy a predetermined relationship with the input signal, the control circuit including a first cumulative adder for performing cumulative summation of updating amounts of the control parameters for a plurality of proposition patterns supplied as the input signal during learning, and a second cumulative adder for adding currently used control parameter values to values obtained by the first cumulative adder to obtain new control parameter values.

Abstract: A multi-layer perceptron circuit device using integrated configuration which is capable of incorporating self-learning function and which is easily extendable. The device includes: at least one synapse blocks containing: a plurality of synapses for performing weight calculation on input signals to obtain output signals, which are arranged in planar array defined by a first and a second directions; input signal lines for transmitting the input signals to the synapses, arranged along the first direction; and output signal lines for transmitting the output signal from the synapses, arranged along the second direction not identical to the first direction; at least one input neuron blocks containing a plurality of neurons to be connected with the input signal lines; and at least one output neuron blocks containing a plurality of neurons to be connected with the output signal lines.

Abstract: A solid state image sensing device of this invention includes signal charge storage units, arranged in a matrix form on a semiconductor substrate, for storing a signal charge generated by photoelectric conversion, signal charge reading units for reading out the signal charge from the signal charge storage units, a pixel signal processing unit, provided in each of a plurality of blocks obtained by dividing the matrix arrangement of the signal charge storage units, for detecting a luminance to output a control signal corresponding to the luminance, a signal charge extracting unit provided adjacent to each of the signal charge storage units and controlled by the control signal obtained in a corresponding block to extract an excessive signal charge from the signal charge storage unit of the block, and coupling elements for connecting adjacent pixel signal processing units.

Abstract: A multi-layer perceptron circuit device using integrated configuration which is capable of incorporating self-learning function and which is easily extendable. The device includes: at least one synapse blocks containing: a plurality of synapses for performing weight calculation on input signals to obtain output signals, which are arranged in planar array defined by a first and a second directions; input signal lines for transmitting the input signals to the synapses, arranged along the first direction; and output signal lines for transmitting the output signal from the synapses, arranged along the second direction not identical to the first direction; at least one input neuron blocks containing a plurality of neurons to be connected with the input signal lines; and at least one output neuron blocks containing a plurality of neurons to be connected with the output signal lines.

Abstract: A Booth's algorithm conversion circuit having first and second switches controlled by input signals QX and Q2X and receiving as input, signals X.sub.i of a logic level positioned in the i digit order of a multiplicand X and signal X.sub.i-1 of a logic level positioned in the i-1 digit order of multiplicand X. The outputs of the first and second switches are tied together and to ground via first and second transitors controlled by signals QX and Q2X, the first and second transistors conducting in an inverse relationship to the first and second switch circuits. The common output of the first and second switch circuits is input to an exclusive OR circuit which receives an additional logic 1 or logic 0 input signal to produce the Booth's converted output. The resulting number of circuit elements and gates provides a simplified, high speed and small circuit for producing the Booth's conversion.

Abstract: A high-speed full adder circuit comprising a plurality of differential transistor pairs and operating at multiple logic levels. This full adder can be made up of basic logic circuits, each having differential transistor pairs, such as exclusive-OR circuits, AND circuits and OR circuits. To reduce the chip size of the full adder, while ensuring a high-speed operation, transistors which may be used in common are replaced by a smaller number of transistors, thereby reducing the number of required transistors.