Patents by Inventor Yukio Katamura

Yukio Katamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230411287
    Abstract: A semiconductor device includes a wiring layer; a first stacked body disposed on the wiring layer; a second stacked body disposed on the first stacked body in a stacking direction; and a first resin body disposed around a periphery of the first stacked body. The first stacked body includes a first pad electrically connected to the wiring layer, a first device layer electrically connected to the first pad, and a first electrode electrically connected to the first device layer. The second stacked body includes a second pad electrically connected to the first electrode and a second device layer electrically connected to the second pad. In the stacking direction, the first resin body is vertically located closer to the wiring layer than an interface between the first stacked body and the second stacked body.
    Type: Application
    Filed: March 3, 2023
    Publication date: December 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Eiichi SHIN, Satoshi HONGO, Susumu YAMAMOTO, Yukio KATAMURA, Gen TOYOTA, Tsutomu FUJITA
  • Publication number: 20230101002
    Abstract: A semiconductor device including a base substrate B, which includes wire layers, chips C1, C2, C3, C4, C5, and C6 provided on the base substrate B, and a protective film P provided on each of the side faces of the chips C1, C2, C3, C4, C5, and C6.
    Type: Application
    Filed: March 14, 2022
    Publication date: March 30, 2023
    Applicant: Kioxia Corporation
    Inventors: Gen TOYOTA, Satoshi HONGO, Tatsuo MIGITA, Susumu YAMAMOTO, Tsutomu FUJITA, Eiichi SHIN, Yukio KATAMURA, Hideki MATSUSHIGE, Kazuki TAKAHASHI
  • Publication number: 20220375901
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of stacked bodies on a substrate, each of the stacked bodies includes a plurality of semiconductor chips. The method further includes forming a plurality of first wires on the stacked bodies. The first wires connecting the stacked bodies to each other. The method further includes forming a resin layer on the stacked bodies and the first wires, then thinning he resin layer until the first wires are exposed.
    Type: Application
    Filed: February 28, 2022
    Publication date: November 24, 2022
    Inventors: Susumu YAMAMOTO, Tsutomu FUJITA, Takeori MAEDA, Satoshi HONGO, Gen TOYOTA, Eiichi SHIN, Yukio KATAMURA
  • Patent number: 9006029
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8691628
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: April 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8629041
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: January 14, 2014
    Assignees: Kabushiki Kaisha Toshiba, KYOCERA Chemical Corporation
    Inventors: Yasuo Tane, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
  • Publication number: 20120318431
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.
    Type: Application
    Filed: August 30, 2012
    Publication date: December 20, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Patent number: 8276537
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: October 2, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Katamura, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20120149151
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, a bonding layer is formed on a first surface of a chip region of a semiconductor wafer. Semiconductor chips are singulated along a dicing region. The semiconductor chips are stacked stepwise via the bonding layer. In formation of the bonding layer of the semiconductor chip, in at least a part of a first region of the first surface not in contact with the other semiconductor chip in a stacked state, a projected section where the bonding layer is formed thicker than the bonding layer in a second region that is in contact with the other semiconductor chip is provided.
    Type: Application
    Filed: September 6, 2011
    Publication date: June 14, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasuo TANE, Yukio KATAMURA, Atsushi YOSHIMURA, Fumihiro IWAMI
  • Publication number: 20120052627
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device including a semiconductor chip having electrode pads formed on a first major surface and a bonding layer provided on a second major surface, and a substrate having the semiconductor chip mounted on the substrate. The manufacturing method can include applying a fillet-forming material to a portion contacting an outer edge of the second major surface of the semiconductor chip on a front face of the substrate. The method can include bonding the second major surface of the semiconductor chip to the substrate via the bonding layer.
    Type: Application
    Filed: March 21, 2011
    Publication date: March 1, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20110263078
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include die bonding to bond a semiconductor element to a first position of a base member via a bonding layer provided on one surface of the semiconductor element. The method can include wire bonding to connect a terminal formed on the semiconductor element to a terminal formed on the base member by a bonding wire. In addition, the method can include sealing to seal the semiconductor element and the bonding wire. Viscosity of the bonding layer in the bonding is controlled not to exceed the viscosity of the bonding layer in the sealing.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 27, 2011
    Applicants: KYOCERA CHEMICAL CORPORATION, Kabushiki Kaisha Toshiba
    Inventors: Yasuo TANE, Yukio Katamura, Atsushi Yoshimura, Fumihiro Iwami, Kazuyoshi Sakurai
  • Publication number: 20110263131
    Abstract: In one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include, upon attaching a bonding material containing a resin and a solvent to a second surface opposed to a first surface including a circuit pattern of a wafer, heating the bonding material to evaporate the solvent and decreasing vapor pressure of the solvent in an atmosphere faced with the bonding material and heating the attached bonding material to form a bonding layer.
    Type: Application
    Filed: January 18, 2011
    Publication date: October 27, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukio KATAMURA, Yasuo Tane, Atsushi Yoshimura, Fumihiro Iwami
  • Publication number: 20110263133
    Abstract: A semiconductor device manufacturing apparatus includes: an accommodation section accommodating an application object; an irradiation section irradiating the application object taken out from the accommodation section with ultraviolet light; an application section including a stage allowing the application object to be placed thereon and an application head discharging a plurality of droplets of an adhesive to the application object placed on the stage, the application section applying the adhesive through the application head to the application object which is irradiated by ultraviolet light through the irradiation section and is placed on the stage; a drying section drying the adhesive applied on the application object with heat; and a transport section including a hand supporting the application object, the transport section which is capable of transporting the application object accommodated in the accommodation section to the irradiation section, the application section, and the drying section.
    Type: Application
    Filed: April 22, 2011
    Publication date: October 27, 2011
    Applicants: Kabushiki Kaisha Toshiba, SHIBAURA MECHATRONICS CORPORATION
    Inventors: Satoru Hara, Shingo Tamai, Akihiro Shigeyama, Michio Ogawa, Hitoshi Aoyagi, Hiroyuki Tanaka, Yasuo Tane, Yukio Katamura
  • Publication number: 20110263097
    Abstract: According to one embodiment, a method for manufacturing semiconductor device can include forming a groove with a depth shallower than a thickness of a wafer. The method can include attaching a surface protection tape via a first bonding layer provided in the surface protection tape. The method can include grinding a surface of the wafer to divide the wafer into a plurality of semiconductor elements. The method can include forming an element bonding layer by attaching a bonding agent and turning the attached bonding agent into a B-stage state. The method can include attaching a dicing tape via a second bonding layer provided in the dicing tape. The method can include irradiating the first bonding layer with a first active energy ray. The method can include removing the surface protection tape. The method can include irradiating the second bonding layer with a second active energy ray.
    Type: Application
    Filed: March 22, 2011
    Publication date: October 27, 2011
    Inventors: Atsushi YOSHIMURA, Yasuo TANE, Yukio KATAMURA, Fumihiro IWAMI
  • Publication number: 20110176346
    Abstract: According to one embodiment, semiconductor memory device including: a circuit substrate in which a circuit pattern is formed; a plurality of semiconductor memories mounted via a solder on both surfaces of the circuit substrate; a connector disposed at one end part of the circuit substrate for connection with a host device; and a resin mold part that seals the both surfaces of the circuit substrate. The resin mold part does not seal a region in which the connector is disposed and collectively seals regions in which the plurality of semiconductor memories are disposed.
    Type: Application
    Filed: January 14, 2011
    Publication date: July 21, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yukio KATAMURA