Patents by Inventor Yukio Koike

Yukio Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12159148
    Abstract: The present invention includes a memory and a processor configured to store, in a storage, a first digital twin in which at least one model defining at least one function of an entity at a given time, and at least one piece of second data that includes, as a constituent element, first data for realizing the function of the entity due to being input to the model are included, create at least one second digital twin by performing predetermined first computation using, as a computation target, at least one first digital twin stored in the storage, and execute computation for arranging the second digital twin in a sandbox for which a predetermined time axis has been set, and realizing a function of an entity indicated by the second digital twin in the sandbox in accordance with the time axis.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: December 3, 2024
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Yasuhiro Iida, Ryutaro Kawamura, Masayuki Hanadate, Koya Mori, Takao Nakamura, Shigekuni Kondo, Yukio Koike, Hiroshi Ogawa, Hiroshi Sakai, Hiroyuki Tanaka
  • Patent number: 11742454
    Abstract: A method for manufacturing a concentrator photovoltaic module including: power generating elements whereon sunlight is concentrated by condenser lenses; and a housing accommodating the power generating elements. The housing includes a resin frame body, a metal bottom plate closing a bottom-side opening of the frame body and an inner surface wherein power generating elements are disposed. The method includes: a peripheral edge of the inner surface of the bottom plate connected to a bottom end surface of the frame body, fixing the bottom plate to the frame body creating the housing; and fixing the housing to a transport jig for transporting the housing horizontally. The transport jig includes a support portion corresponding to the bottom end surface of the frame body, and supports the housing. The housing is fixed to the transport jig, with the support portion attached to a peripheral edge of an outer surface of the bottom plate.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 29, 2023
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Yukio Koike, Kenji Saito, Ryusuke Imai
  • Patent number: 7690326
    Abstract: A system for controlling the coating width of an electrode plate, The system includes: a coating device which ejects a paste at a predetermined width from each of a plurality of slit nozzles toward a fed core substrate to form a coating layer on the surface of the core substrate; a gap controlling device which controls the gap between the slit nozzles of the coating device and the core substrate; a coating width measuring device which measures the width of the coating layer on the surface of the core substrate; and a controlling unit which controls the gap controlling device based on the results obtained by comparing the measured coating width with a predetermined coating width. In this system, the stripe-shaped coating layer is formed without using a masking tape, and the width of the coating layer is controlled with high accuracy.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 6, 2010
    Assignee: Panasonic Corporation
    Inventors: Yutaka Wakai, Kaoru Okinaga, Yukio Koike, Tomofumi Yanagi
  • Publication number: 20070248745
    Abstract: A system for controlling the coating width of an electrode plate, The system includes; a coating device which ejects a paste at a predetermined width from each of a plurality of slit nozzles toward a fed core substrate to form a coating layer on the surface of the core substrate; a gap controlling device which controls the gap between the slit nozzles of the coating device and the core substrate; a coating width measuring device which measures the width of the coating layer on the surface of the core substrate; and a controlling unit which controls the gap controlling device based on the results obtained by comparing the measured coating width with a predetermined coating width. In this system, the stripe-shaped coating layer is formed without using a masking tape, and the width of the coating layer is controlled with high accuracy.
    Type: Application
    Filed: March 23, 2007
    Publication date: October 25, 2007
    Inventors: Yutaka Wakai, Kaoru Okinaga, Yukio Koike, Tomofumi Yanagi
  • Patent number: 6387445
    Abstract: A tungsten layer is formed on the surface of an object to be treated (e.g., a semiconductor wafer), supplying a process gas which includes a material gas of a tungsten fluoride (e.g., WF6) gas and a reducing gas (e.g., H2 gas) for reducing the material gas. In this case, an intermediate tungsten film forming step is carried out between a nuclear crystalline film forming step of forming a nuclear crystalline film of tungsten on the surface of the object and a main tungsten film forming step of forming a main tungsten film on the nuclear crystalline film. At the intermediate tungsten film forming step, an intermediate tungsten film is formed while the flow ratio of the material gas to the reducing gas is smaller than that at the main tungsten film forming step. Thus, the incubation time T2 after the deposition of the nuclear crystalline film is removed, so that it is possible to enhance the whole mean deposition rate and to improve the uniformity of the thickness between objects to be processed.
    Type: Grant
    Filed: September 13, 2000
    Date of Patent: May 14, 2002
    Assignee: Tokyo Electron Limited
    Inventors: Yasushi Aiba, Yukio Koike
  • Patent number: 5727604
    Abstract: Weight of the paste (21) per area is measured continuously without contact by irradiating the belt-shaped paste-coated punched metal electrode (41) with .beta. ray (51), during running of the electrode (41) on a production line, then trapping dosage of the .beta. ray radiation transmitted through the electrode (41) by an ionization chamber (4b, 50), followed by processing the measured value in a micro-processor unit (6) on the basis of comparing with a previously determined reference value. BY means of the output signal from the processor (6), the gap of slit (24) between the blades (23a and 23b) is feedback-controlled, so as to control thickness, hence weight per unit area of the pasty mixture uniform.
    Type: Grant
    Filed: July 27, 1995
    Date of Patent: March 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Koike, Chitoshi Hara, Masao Nakamura, Mitsuyoshi Kio, Tetsushiro Torigoe
  • Patent number: 5148034
    Abstract: A method of ion implantation of a semiconductor devices to neutralize electrostatic charge stored on a wafer. Neutralizing electrons are supplied to a passage through which a positive ion beam is passed while forming a barrier of negative electrostatic potential between an area in the passage to which the neutralizing electrons are supplied and the wafer. When the positive ion beam is not present in the passage, the potential of the barrier is set lower than the negative potential corresponding to energy held in the neutralizing electrons. When the beam is not passed through the passage, most of the neutralizing electrons cannot cross over the barrier, but when the beam is passed through the passage, most of the electrons can cross over the barrier, following it, to shower over the wafer.
    Type: Grant
    Filed: April 19, 1990
    Date of Patent: September 15, 1992
    Assignee: Tokyo Electron Limited
    Inventor: Yukio Koike
  • Patent number: 4794374
    Abstract: An A/D converter comprises a resistor ladder connected between first and second reference potentials so that each connection tap provides a different divided reference potential. A plurality of first switches are each connected at their one end to one connection tap of the resistor ladder and at their other end to a corresponding number of common connection nodes. Also, a plurality of second switches are each connected at their one end commonly to an input for an analog voltage signal and at their other end to the corresponding common connection nodes. Each of the nodes is connected through one coupling capacitor to one amplifier having adapted to generate an output signal representative of whether the voltage of the input signal is higher or lower than a voltage appearing at the above mentioned one connection tap of the resistor ladder.
    Type: Grant
    Filed: May 4, 1987
    Date of Patent: December 27, 1988
    Assignee: NEC Corporation
    Inventor: Yukio Koike