Abstract: An apparatuses includes a processor, a storage unit, and a communication unit to access the storage unit without intermediary of the processor and to access a second apparatus of the plurality of information processing apparatuses via a communication unit of the second apparatus. The communication unit of a first apparatus of the plurality of information processing apparatuses executes at least one of a process of storing redundant data which is generated by making redundant data stored in the storage unit of the first apparatus in the storage unit of the second apparatus via the communication unit of the second apparatus, and a process of acquiring redundant data which is generated by making redundant data stored in the storage unit of the second apparatus via the communication unit of the second apparatus, and storing the acquired data in the storage unit of the first apparatus.

Abstract: An apparatuses includes a processor, a storage unit, and a communication unit to access the storage unit without intermediary of the processor and to access a second apparatus of the plurality of information processing apparatuses via a communication unit of the second apparatus. The communication unit of a first apparatus of the plurality of information processing apparatuses executes at least one of a process of storing redundant data which is generated by making redundant data stored in the storage unit of the first apparatus in the storage unit of the second apparatus via the communication unit of the second apparatus, and a process of acquiring redundant data which is generated by making redundant data stored in the storage unit of the second apparatus via the communication unit of the second apparatus, and storing the acquired data in the storage unit of the first apparatus.

Abstract: A layout method for a semiconductor integrated circuit includes, generating logic cell layout data by arranging logic cells and signal lines connected to said logic cells, by using an automatic place and root tool, generating variable capacitor cell layout data by arranging variable capacitor cells and control lines for controlling capacitance value of the variable capacitor cells, by using the automatic place and root tool, and generating layout data of the semiconductor integrated circuit, based on the logic cell layout data and the variable capacitor cell layout data. The generating variable capacitor cell layout data includes, arranging the control lines so as to be same as said signal lines in a resistance of a unit length in one wiring layer.

Abstract: To maintain the noise removal characteristic of a Schmidt trigger circuit stably. There are provided a Schmidt trigger circuit 10 constituted from a Vp/Vn setting unit 11 for determining the threshold level of an input signal and an RS latch unit 12, a driver unit 13 having a low-pass filter function of passing a pulse signal with a predetermined width or more, output from the Schmidt trigger circuit 10, and an operating current setting and sensor unit 14 for changing a supply voltage and supplying the changed supply voltage to an inverter INV4 having the low-pass filter function so that the inverter INV4 changes the width of a pulse to be passed through. The operating current setting and sensor unit 14 includes a sensor circuit 16 having a P-ch transistor MP2 and an N-ch transistor MN2 that are connected in series for setting the supply voltage.

Abstract: A level shifter has a voltage converting circuit converting an input signal provided by a first power supply into an output signal provided by a second power supply, and a reset circuit outputting a reset signal when the first power supply is turned off. The voltage converting circuit has: first and second FETs which are cross-coupled; a first trigger FET connected to the second FET and triggering it in response to the input signal; a second trigger FET connected to the second FET in parallel with the first trigger FET; a third trigger FET connected to the first FET and triggering it in response to an inversion signal of the input signal; and a fourth trigger FET connected to the first FET in parallel with the third trigger FET. Any of the second and the fourth trigger FETs triggers corresponding one of the second FET and the first FET in response to the reset signal.

Abstract: To maintain the noise removal characteristic of a Schmidt trigger circuit stably. There are provided a Schmidt trigger circuit 10 constituted from a Vp/Vn setting unit 11 for determining the threshold level of an input signal and an RS latch unit 12, a driver unit 13 having a low-pass filter function of passing a pulse signal with a predetermined width or more, output from the Schmidt trigger circuit 10, and an operating current setting and sensor unit 14 for changing a supply voltage and supplying the changed supply voltage to an inverter INV4 having the low-pass filter function so that the inverter INV4 changes the width of a pulse to be passed through. The operating current setting and sensor unit 14 includes a sensor circuit 16 having a P-ch transistor MP2 and an N-ch transistor MN2 that are connected in series for setting the supply voltage.

Abstract: A level shifter has a voltage converting circuit converting an input signal provided by a first power supply into an output signal provided by a second power supply, and a reset circuit outputting a reset signal when the first power supply is turned off. The voltage converting circuit has: first and second FETs which are cross-coupled; a first trigger FET connected to the second FET and triggering it in response to the input signal; a second trigger FET connected to the second FET in parallel with the first trigger FET; a third trigger FET connected to the first FET and triggering it in response to an inversion signal of the input signal; and a fourth trigger FET connected to the first FET in parallel with the third trigger FET. Any of the second and the fourth trigger FETs triggers corresponding one of the second FET and the first FET in response to the reset signal.