Patents by Inventor Yukio Muroi

Yukio Muroi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110263126
    Abstract: Method for manufacturing a silicon wafer free of point defect agglomerates by processes including adding pure carbon to raw material of polycrystalline silicon, melting to become a molten silicon liquid, pulling a single silicon crystal ingot comprising a perfect domain [P] from the molten silicon liquid by controlling a ratio of V/G (mm2/minute ° C.), lapping a silicon wafer cut out from the ingot, beveling the silicon wafer, chemical etching the beveled wafer so as to be removed damages of a surface of the wafer, and mirror-polishing the etched wafer, and the pure carbon is added to the raw material of polycrystalline silicon so that a density of carbon in the ingot becomes 1×1015 to 5×1015 atoms/cm3.
    Type: Application
    Filed: April 29, 2011
    Publication date: October 27, 2011
    Applicant: SUMCO CORPORATION
    Inventors: Kazuhiro HARADA, Hisashi Furuya, Yukio MUROI
  • Patent number: 6682597
    Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.
    Type: Grant
    Filed: June 3, 2002
    Date of Patent: January 27, 2004
    Assignee: Mitsubishi Materials Silicon Corporation
    Inventors: Hiroshi Koya, Hisashi Furuya, Yoji Suzuki, Yukio Muroi, Takaaki Shiota
  • Publication number: 20030051660
    Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.
    Type: Application
    Filed: June 3, 2002
    Publication date: March 20, 2003
    Inventors: Hiroshi Koya, Hisashi Furuya, Yoji Suzuki, Yukio Muroi, Takaaki Shiota
  • Patent number: 6428619
    Abstract: A method of heat-treating a silicon wafer has the steps of: preparing a silicon wafer having an oxygen concentration of 1.2×1018 atoms/cm3 or less (old ASTM) without generating crystal originated particles(COP'S) and interstitial-type large dislocation(L/D); forming a polysilicon layer of 0.1 &mgr;m to 1.6 &mgr;m in thickness on a back of the silicon wafer by a chemical-vapor deposition at a temperature of 670° C.±30° C.; and heat-treating the silicon wafer having the polysilicon layer in an oxygen atmosphere at 1000° C.±30° C. for 2 to 5 hours and subsequently at 1130° C.±30° C. for 1 to 16 hours. In this method, the silicon wafer before the formation of the polysilicon layer thereon is the type of a wafer in which oxidation induced stacking faults(OSF's) manifest itself at a center of the wafer when the wafer is subjected to the heat-treatment.
    Type: Grant
    Filed: October 23, 2000
    Date of Patent: August 6, 2002
    Assignee: Mitsubishi Materials Silicon Corporation
    Inventors: Hiroshi Koya, Hisashi Furuya, Yoji Suzuki, Yukio Muroi, Takaaki Shiota