Abstract: An indoor unit of an air-conditioning apparatus including a body placed on a wall surface of a room that is an air-conditioned space, the indoor unit including a temperature sensor disposed at a position projecting from the body, and including a temperature detector that detects a temperature based on heat radiation from a target and a motor that causes the temperature detector to rotate, the position being a place where the temperature sensor is capable of detecting a temperature in all the horizontal directions by rotating the temperature detector.

Abstract: An indoor unit of an air-conditioning apparatus including a body placed on a wall surface of a room that is an air-conditioned space, the indoor unit including a temperature sensor disposed at a position projecting from the body, and including a temperature detector that detects a temperature based on heat radiation from a target and a motor that causes the temperature detector to rotate, the position being a place where the temperature sensor is capable of detecting a temperature in all the horizontal directions by rotating the temperature detector.

Abstract: A nonwoven fabric which contains pitch-based carbon fibers having a high elongation and a high elastic modulus which are not attained in the prior art and is obtained by improving the tensile elongation of carbon fibers derived from mesophase pitch, a felt obtained from the nonwoven fabric, and production processes therefore. The nonwoven fabric contains pitch-based carbon fibers, wherein the pitch-based carbon fibers have (i) an average fiber diameter (D1) measured by an optical microscope of more than 2 ?m and 20 ?m or less, (ii) a percentage of the degree of fiber diameter distribution (S1) to average fiber diameter (D1) measured by an optical microscope of 3 to 20%, (iii) a tensile elastic modulus of 80 to 300 GPa and (iv) a tensile elongation of 1.4 to 2.5%.

Abstract: A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

Abstract: A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

Abstract: A nonvolatile semiconductor memory device selects a bit line while a word line is in a non-selected state, and self-selectively writes back only a cell in an overerased state on the selected bit line. The nonvolatile semiconductor memory device performs this write-back operation after completion of erase verification. At this time, current sensitivity of a sense current amplifier defining the threshold of a memory cell is set in view of an off-state leakage current of a memory cell transistor.

Abstract: A memory test device that issues a test pattern read request to a memory, captures test pattern signals placed by the memory on a data input/output bus in response to the test pattern read request, and compares the test pattern signals with their expected values. This can solve a problem involved in a conventional memory test device in that because the pin width of data pins is narrower than the bus width of the data input/output bus that connects a memory and a data bus controller, even if the memory reads test pattern signals in accordance with the width of the data input/output bus, the test pattern signals cannot be sent to the tester without being divided, and hence the tester cannot achieve the quick test of the memory.

Abstract: A multiprocessor system having a plurality of processor units each including a CPU and a local cache memory connected to the CPU. The CPUs have their shared bus terminals connected to a global shared bus, and the local cache memories have their bus terminals connected to a global unshared bus. The global shared bus is connected to an external shared memory for storing shared information used in common by the CPUs, and the global unshared bus is connected to an external unshared memory for storing unshared information used by the CPUs. This configuration can solve a problem of a conventional multiprocessor system in that it takes a rather long time for a cache memory to monitor write operations of the other cache memories, its processing speed is reduced because write back caches cannot be used, and its cost is increased because inexpensive caches cannot be used.