Patents by Inventor Yukio Nishiyama

Yukio Nishiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7446061
    Abstract: A semiconductor substrate with a groove is placed in a plasma generating reaction chamber. Silicon, oxygen and hydrogen containing gases are introduced into the reaction chamber as process gases. A ratio of a gas flow of the hydrogen containing gas except the silicon containing gas to a total gas flow of the silicon containing gas and the oxygen containing gas defines a first gas-flow ratio. A ratio of a gas flow of the oxygen containing gas to that of the silicon containing gas defines a second gas-flow ratio. The first and second gas-flow ratios establish a linear function for a critical condition. A cluster formation condition is set up by relatively increasing the first gas-flow ratio while relatively decreasing the second gas-flow ratio with respect to the critical condition. A cluster suppression condition is also set up by relatively decreasing the first gas-flow ratio while relatively increasing the second gas-flow ratio with respect to the critical condition.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: November 4, 2008
    Assignee: Kabushiki Kaihsa Toshiba
    Inventors: Hiroshi Sato, Rempei Nakata, Yukio Nishiyama, Taketo Matsuda
  • Patent number: 7371654
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: May 13, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
  • Publication number: 20080009143
    Abstract: Disclosed is a method of forming a silicon oxide layer comprising: supplying at least a gas containing Si as a raw gas to a semiconductor substrate having a recess formed on its surface to form a primary reactant on the surface, then performing dehydration condensation to form a silicon oxide layer above the semiconductor substrate; removing a part of the silicon oxide layer until a portion of the silicon oxide layer formed in the recess that has a lower density than the silicon oxide layer formed in a vicinity of the surface is at least partially exposed; and supplying a gas containing Si to the silicon oxide layer having a lower density.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 10, 2008
    Inventors: Nobuhide Yamada, Rempei Nakata, Yukio Nishiyama
  • Patent number: 7247888
    Abstract: There is here disclosed a film forming ring including a ring main body being made of an insulating material and formed in an annular shape along an edge of a substrate on which a film forming process by using a material gas in a plasma state is applied, and an inner rim of the ring main body being formed higher than its outside portion.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: July 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hirotaka Ogihara, Yukio Nishiyama, Akio Ui, Takashi O
  • Publication number: 20070128865
    Abstract: A semiconductor substrate with a groove is placed in a plasma generating reaction chamber. Silicon, oxygen and hydrogen containing gases are introduced into the reaction chamber as process gases. A ratio of a gas flow of the hydrogen containing gas except the silicon containing gas to a total gas flow of the silicon containing gas and the oxygen containing gas defines a first gas-flow ratio. A ratio of a gas flow of the oxygen containing gas to that of the silicon containing gas defines a second gas-flow ratio. The first and second gas-flow ratios establish a linear function for a critical condition. A cluster formation condition is set up by relatively increasing the first gas-flow ratio while relatively decreasing the second gas-flow ratio with respect to the critical condition. A cluster suppression condition is also set up by relatively decreasing the first gas-flow ratio while relatively increasing the second gas-flow ratio with respect to the critical condition.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 7, 2007
    Inventors: Hiroshi Sato, Rempei Nakata, Yukio Nishiyama, Taketo Matsuda
  • Publication number: 20060189092
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Application
    Filed: April 3, 2006
    Publication date: August 24, 2006
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
  • Patent number: 7052971
    Abstract: A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nishiyama, Hirotaka Ogihara, Rempei Nakata
  • Patent number: 6951807
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating layer formed above the semiconductor substrate, a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer, a diffusion preventive layer formed on at least the first metal interconnection to prevent diffusion of a metal included in the first metal interconnection, a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer, a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer, and a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: October 4, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Watanabe, Yukio Nishiyama
  • Publication number: 20050191811
    Abstract: There is here disclosed a film forming ring comprising a ring main body being made of an insulating material and formed in an annular shape along an edge of a substrate on which a film forming process by using a material gas in a plasma state is applied, and an inner rim of the ring main body being formed higher than its outside portion.
    Type: Application
    Filed: February 28, 2005
    Publication date: September 1, 2005
    Inventors: Hirotaka Ogihara, Yukio Nishiyama, Akio Ui, Takashi O
  • Patent number: 6798038
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
  • Publication number: 20040173870
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Application
    Filed: March 15, 2004
    Publication date: September 9, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
  • Publication number: 20040072418
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating layer formed above the semiconductor substrate, a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer, a diffusion preventive layer formed on at least the first metal interconnection to prevent diffusion of a metal included in the first metal interconnection, a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer, a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer, and a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.
    Type: Application
    Filed: September 24, 2003
    Publication date: April 15, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kei Watanabe, Yukio Nishiyama
  • Patent number: 6646351
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating layer formed above the semiconductor substrate, a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer, a diffusion preventive layer formed on at least the first metal interconnection to prevent diffusion of a metal included in the first metal interconnection, a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer, a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer, and a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: November 11, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Watanabe, Yukio Nishiyama
  • Publication number: 20030052384
    Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.
    Type: Application
    Filed: May 9, 2002
    Publication date: March 20, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
  • Publication number: 20030022522
    Abstract: A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.
    Type: Application
    Filed: July 12, 2002
    Publication date: January 30, 2003
    Inventors: Yukio Nishiyama, Hirotaka Ogihara, Rempei Nakata
  • Publication number: 20030020168
    Abstract: A semiconductor device comprises a semiconductor substrate, an interlayer insulating layer formed above the semiconductor substrate, a first metal interconnection embedded in the interlayer insulating layer with a surface thereof exposed to the same plane as a surface of the interlayer insulating layer, a diffusion preventive layer formed on at least the first metal interconnection to prevent diffusion of a metal included in the first metal interconnection, a nitrogen-doped silicon oxide layer formed on the diffusion preventive layer, a fluorine-doped silicon oxide layer formed on the nitrogen-doped silicon oxide layer, and a second metal interconnection embedded in the fluorine-doped silicon oxide layer with a surface thereof exposed to the same plane as a surface of the fluorine-doped silicon oxide layer, and electrically connected to the first metal interconnection.
    Type: Application
    Filed: July 25, 2002
    Publication date: January 30, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kei Watanabe, Yukio Nishiyama
  • Patent number: 6153509
    Abstract: In a method of manufacturing a semiconductor device including a semiconductor element formed on a semiconductor substrate, an SiOF film is formed at least on the top surfaces of metal wirings under condition that an in-chamber pressure is 5 mTorr or lower. The SiOF film can thus be buried into a space between the metal wirings without causing any void and the capacitance between the wirings can be prevented from increasing, while preventing the metal wirings from being damaged and preventing the aspect ratio from increasing.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Watanabe, Yukio Nishiyama, Naruhiko Kaji, Hideshi Miyajima
  • Patent number: 5641581
    Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4, P.ltoreq.10.sup.-1.times.10.sup.-E/45( A)and the relationship between the ion energy E (eV) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11.times.10.sup.-E/45, 10 .ltoreq.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: June 24, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nishiyama, Rempei Nakata, Nobuo Hayasaka, Haruo Okano, Riichirou Aoki, Takahito Nagamatsu, Akemi Satoh, Masao Toyosaki, Hitoshi Ito
  • Patent number: 5571578
    Abstract: A plasma CVD device having a chamber, an upper electrode provided in the chamber, an under electrode provided in the chamber to be opposite to the upper electrode and to mount a sample thereon, and a plurality of power sources having a different frequency connected to the upper electrode. Gas is introduced into the chamber of the plasma CVD device, the gas contains at least an organic silicon compound, CF.sub.4 and O.sub.2, and has an element ratio (F/Si) of silicon (Si), constituting the organic silicon compound, to fluorine (F), constituting CF.sub.4, to be set to 15 or more. Si(OC.sub.2 H.sub.5).sub.4 or Si(OCH.sub.3).sub.4 is used as an organic silicon compound.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: November 5, 1996
    Assignee: Kabushiki Kaisha Tohsiba
    Inventors: Naruhiko Kaji, Riichirou Aoki, Hiroyuki Toyama, Hidemitsu Egawa, Takamitsu Yoshida, Yukio Nishiyama
  • Patent number: 5429995
    Abstract: Disclosed is a method of manufacturing a semiconductor device, in which a silicon oxide film containing fluorine, said film exhibiting a low dielectric constant and a low hygroscopicity and acting as an insulating film for electrically isolating wirings included in a semiconductor device, is formed by a plasma CVD method using a source gas containing at least silicon, oxygen and fluorine, under the conditions that the relationship between the gas pressure P (Torr) and the ion energy E (eV) satisfies formula A given below:P.gtoreq.5.times.10.sup.-4,P.ltoreq.10.sup.-1 .times.10.sup.-E/45(A)and the relationship between the ion energy E (ev) and the plasma density D (/cm.sup.3) satisfies the formula B given below:D.gtoreq.2.times.10.sup.11 .times.10.sup.-E/45, 10.ltoreq.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: July 4, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nishiyama, Rempei Nakata, Nobuo Hayasaka, Haruo Okano, Riichirou Aoki, Takahito Nagamatsu, Akemi Satoh, Masao Toyosaki, Hitoshi Ito