Patents by Inventor Yukio Okazaki

Yukio Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10761201
    Abstract: An object detection device includes: a classifier that receives, from a radar device that transmits a transmission wave and receives a reflected wave that is the transmission wave reflected by an object around a subject vehicle, detection result information indicative of an intensity, an azimuth, and a Doppler velocity obtained from a Doppler frequency shift of the reflected wave, and determines whether the detection result information is first detection result information corresponding to a moving object or second detection result information corresponding to a still object; a calculator that calculates distances from the radar device to reflection points of the moving object on the basis of the first detection result information; and an output that supplies, to a predetermined device, first reflection point information indicating the distances of the reflection points and azimuths of the reflection points based on the radar device.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 1, 2020
    Assignee: Panasanic Intellectul Property Management Co., Ltd.
    Inventors: Yukio Okazaki, Hirofumi Nishimura, Asako Hamada
  • Patent number: 10243640
    Abstract: Provided is a phased array transmission device including: a plurality of transmission branches, each being provided with a phase shift unit that applies a phase rotation to a baseband signal, a DC offset correction unit that adds a first correction value to an output signal of the phase shift unit, and a mixer that subjects an output signal of the DC offset correction unit to a frequency conversion to a high frequency band; and a correction control unit that calculates a second correction value with which a carrier leak component included in an output signal of the mixer is minimized, for each of a plurality of candidates for a phase rotation amount that is set for the phase rotation, and determines the first correction value on the basis of the second correction value.
    Type: Grant
    Filed: March 9, 2017
    Date of Patent: March 26, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kenji Miyanaga, Yukio Okazaki
  • Publication number: 20180172814
    Abstract: An object detection device includes: a classifier that receives, from a radar device that transmits a transmission wave and receives a reflected wave that is the transmission wave reflected by an object around a subject vehicle, detection result information indicative of an intensity, an azimuth, and a Doppler velocity obtained from a Doppler frequency shift of the reflected wave, and determines whether the detection result information is first detection result information corresponding to a moving object or second detection result information corresponding to a still object; a calculator that calculates distances from the radar device to reflection points of the moving object on the basis of the first detection result information; and an output that supplies, to a predetermined device, first reflection point information indicating the distances of the reflection points and azimuths of the reflection points based on the radar device.
    Type: Application
    Filed: December 7, 2017
    Publication date: June 21, 2018
    Inventors: YUKIO OKAZAKI, HIROFUMI NISHIMURA, ASAKO HAMADA
  • Publication number: 20170346468
    Abstract: A radar apparatus includes a transmitter including a plurality of circuits that intermittently transmit one or more radar signals, the plurality of circuits being suspended power supplying during a period in which the one or more radar signals are not transmitted, variation detection circuitry that detects process variations of the plurality of circuits, and determination circuitry that determines a startup timing of each of the plurality of circuits in response to the process variations and outputs startup commands in response to the determined startup timings to the plurality of circuits.
    Type: Application
    Filed: May 19, 2017
    Publication date: November 30, 2017
    Inventors: YUKIO OKAZAKI, KAZUTOSHI SATOU, NORIAKI SAITO
  • Publication number: 20170288762
    Abstract: Provided is a phased array transmission device including: a plurality of transmission branches, each being provided with a phase shift unit that applies a phase rotation to a baseband signal, a DC offset correction unit that adds a first correction value to an output signal of the phase shift unit, and a mixer that subjects an output signal of the DC offset correction unit to a frequency conversion to a high frequency band; and a correction control unit that calculates a second correction value with which a carrier leak component included in an output signal of the mixer is minimized, for each of a plurality of candidates for a phase rotation amount that is set for the phase rotation, and determines the first correction value on the basis of the second correction value.
    Type: Application
    Filed: March 9, 2017
    Publication date: October 5, 2017
    Inventors: KENJI MIYANAGA, YUKIO OKAZAKI
  • Patent number: 9654063
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: May 16, 2017
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yukio Okazaki, Masakatsu Maeda, Shigeki Nakamura, Akinori Daimo
  • Patent number: 9614664
    Abstract: A wireless communication apparatus includes multiple antenna devices, a signal generator, a phase shifter, a phase controller, and a quadrature error corrector (phase error corrector and amplitude error corrector). The signal generating circuitry, in operation, generates an IQ signal having an I signal and a Q signal. The plurality of phase shifting circuitry provided for each of the plurality of antenna devices, in operation, generates a plurality of combination signals by combining the I signal and the Q signal based on a predetermined combining scheme. The phase controlling circuitry, in operation, controls the predetermined combining scheme in each of the plurality of phase shifting circuitry. The quadrature error correcting circuitry, in operation, corrects at least one of amplitude combining scheme and phase combining scheme of the predetermined combining scheme in a correction of the predetermined combining scheme.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: April 4, 2017
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Tadashi Morita, Yukio Okazaki
  • Publication number: 20160352507
    Abstract: A wireless communication apparatus includes multiple antenna devices, a signal generator, a phase shifter, a phase controller, and a quadrature error corrector (phase error corrector and amplitude error corrector). The signal generating circuitry, in operation, generates an IQ signal having an I signal and a Q signal. The plurality of phase shifting circuitry provided for each of the plurality of antenna devices, in operation, generates a plurality of combination signals by combining the I signal and the Q signal based on a predetermined combining scheme. The phase controlling circuitry, in operation, controls the predetermined combining scheme in each of the plurality of phase shifting circuitry. The quadrature error correcting circuitry, in operation, corrects at least one of amplitude combining scheme and phase combining scheme of the predetermined combining scheme in a correction of the predetermined combining scheme.
    Type: Application
    Filed: May 17, 2016
    Publication date: December 1, 2016
    Inventors: TADASHI MORITA, YUKIO OKAZAKI
  • Publication number: 20160142014
    Abstract: A bias circuit comprises: a first circuit that comprises a first resistor and a decoupling capacitor; a bias voltage generation circuit that comprises a first transistor being connected to the first circuit; one or more switches; a first replica circuit comprising a second circuit and a second transistor, the second circuit comprising a second resistor and a capacitor, the second transistor being connected to the second circuit; a second replica circuit comprising a third transistor; a comparator that makes a comparison between a pseudo-bias voltage and a reference voltage; and a control circuit that controls the one or more switches on the basis of the comparison result to reduce the amount of the current flowing through the first transistor.
    Type: Application
    Filed: October 16, 2015
    Publication date: May 19, 2016
    Inventors: YUKIO OKAZAKI, MASAKATSU MAEDA, SHIGEKI NAKAMURA, AKINORI DAIMO
  • Patent number: 9294040
    Abstract: A power amplifier includes an output terminal, capacitive element groups including capacitive elements, and amplifier groups including amplifiers. Capacitive elements of the capacitive element groups are disposed on a first circle whose center is located on the output terminal. Amplifiers of the amplifier groups corresponding to the capacitive elements of the capacitive element groups are disposed on a second circle, which is concentric with and larger than the first circle. Each of the capacitive elements of the capacitive element groups is connected to both the output terminal and the corresponding amplifier of the amplifiers of the amplifier groups.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: March 22, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Yukio Okazaki, Akinori Daimo
  • Publication number: 20160079928
    Abstract: A power amplifier includes an output terminal, capacitive element groups including capacitive elements, and amplifier groups including amplifiers. Capacitive elements of the capacitive element groups are disposed on a first circle whose center is located on the output terminal. Amplifiers of the amplifier groups corresponding to the capacitive elements of the capacitive element groups are disposed on a second circle, which is concentric with and larger than the first circle. Each of the capacitive elements of the capacitive element groups is connected to both the output terminal and the corresponding amplifier of the amplifiers of the amplifier groups.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 17, 2016
    Applicant: PANASONIC CORPORATION
    Inventors: Yukio OKAZAKI, Akinori DAIMO
  • Patent number: 9231526
    Abstract: An SCPA includes a pad, capacitative elements, amplifiers on an IC chip. The capacitative elements are disposed on a first circle whose center is located on the pad. The amplifiers which correspond to the capacitative elements are disposed on a second circle which is a concentric circle larger than the first circle. The pad, each of the capacitative elements, and a corresponding one of the amplifiers are aligned in a line so that the length of wiring is the shortest.
    Type: Grant
    Filed: November 11, 2014
    Date of Patent: January 5, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Yukio Okazaki, Akinori Daimo
  • Publication number: 20150180429
    Abstract: An SCPA includes a pad, capacitative elements, amplifiers on an IC chip. The capacitative elements are disposed on a first circle whose center is located on the pad. The amplifiers which correspond to the capacitative elements are disposed on a second circle which is a concentric circle larger than the first circle. The pad, each of the capacitative elements, and a corresponding one of the amplifiers are aligned in a line so that the length of wiring is the shortest.
    Type: Application
    Filed: November 11, 2014
    Publication date: June 25, 2015
    Inventors: YUKIO OKAZAKI, AKINORI DAIMO
  • Patent number: 7673145
    Abstract: This invention includes an image quality priority level decision processing unit (40) which evaluates the magnitude of an image quality of each of a plurality of first image data formed from biometric images associated with the same target on the basis of a specific index having the relationship of a monotone function with authentication accuracy of biometric authentication, and outputs each of the first image data upon adding a priority level thereto on the basis of the evaluation result, a first image storage (6, 81) unit which stores each of the first image data having a priority level added thereto from the image quality priority level decision processing unit (40), a second image storage unit (8, 61) which stores second image data used for comparison/collation with the first image data, an image collation unit (7) which compares/collates the second image data stored in the second image storage unit (8, 61) with the first image data stored in the first image storage unit (6, 81) and outputs the comparison
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: March 2, 2010
    Assignee: Nippon Telephone and Telegraph Corporation
    Inventors: Takahiro Hatano, Satoshi Shigematsu, Hiroki Morimura, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi
  • Patent number: 7606399
    Abstract: A sensor cell includes a sensor electrode (101) formed on a substrate (100), a signal output unit (16) which outputs a signal corresponding to a capacitance (Cf) formed between the sensor electrode and the surface of a finger (3), a high-sensitivity electrode (103) formed on the substrate so as to be insulated and isolated from the sensor electrode, and a potential controller (14) which controls the potential of the finger surface via a capacitance (Cc) formed between the high-sensitivity electrode and the finger surface by controlling the potential of the high-sensitivity electrode. In this arrangement, when the resistance of the finger is high, the potential of the finger surface can be controlled so as not to fluctuate with the potential change of the sensor electrode.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: October 20, 2009
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Mamoru Nakanishi, Satoshi Shigematsu, Takahiro Hatano, Yukio Okazaki, Katsuyuki Machida
  • Patent number: 7589454
    Abstract: A driving apparatus comprises: an electro-mechanical conversion element; a driving member that drives backwards and forwards in a straight line in response to extension and contraction of the electro-mechanical conversion element which are brought about by a drive signal being supplied thereto; a driven member, frictionally engaged with the driving member, that moves backwards and forwards in a straight line along the driving member by driving the driving member; and a drive control unit that divides a whole traveling area of one or both of an outgoing traveling path and an incoming traveling path of the driven member into a plurality of divided areas and supplies different drive signals to the divided areas so as to implement a drive control.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: September 15, 2009
    Assignee: Fujinon Corporation
    Inventors: Haruo Onozuka, Tatsuo Saito, Katsuji Ozawa, Yukio Okazaki
  • Patent number: 7440534
    Abstract: A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.
    Type: Grant
    Filed: August 9, 2005
    Date of Patent: October 21, 2008
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hiroki Morimura, Satoshi Shigematsu, Yukio Okazaki, Katsuyuki Machida
  • Publication number: 20080056543
    Abstract: A sensor cell includes a sensor electrode (101) formed on a substrate (100), a signal output unit (16) which outputs a signal corresponding to a capacitance (Cf) formed between the sensor electrode and the surface of a finger (3), a high-sensitivity electrode (103) formed on the substrate so as to be insulated and isolated from the sensor electrode, and a potential controller (14) which controls the potential of the finger surface via a capacitance (Cc) formed between the high-sensitivity electrode and the finger surface by controlling the potential of the high-sensitivity electrode. In this arrangement, when the resistance of the finger is high, the potential of the finger surface can be controlled so as not to fluctuate with the potential change of the sensor electrode.
    Type: Application
    Filed: July 15, 2005
    Publication date: March 6, 2008
    Inventors: Hiroki Morimura, Mamoru Nakanishi, Satoshi Shigematsu, Takahiro Hatano, Yukio Okazaki, Katsuyuki Machida
  • Publication number: 20080012619
    Abstract: A master latch (1) is formed from a static circuit, and a slave latch (2) is formed from a dynamic circuit. The number of circuit elements can be smaller as compared to a slave latch formed from a static circuit so that the size and area of a master-slave flip-flop can be reduced. Since the master latch is formed from a static circuit, data can be held stably during the standby time by setting the master latch in a data holding state.
    Type: Application
    Filed: August 9, 2005
    Publication date: January 17, 2008
    Inventors: Hiroki Morimura, Satoshi Shigematsu, Yukio Okazaki, Katsuyuki Machida
  • Publication number: 20070236101
    Abstract: A driving apparatus comprises: an electro-mechanical conversion element; a driving member that drives backwards and forwards in a straight line in response to extension and contraction of the electro-mechanical conversion element which are brought about by a drive signal being supplied thereto; a driven member, frictionally engaged with the driving member, that moves backwards and forwards in a straight line along the driving member by driving the driving member; and a drive control unit that divides a whole traveling area of one or both of an outgoing traveling path and an incoming traveling path of the driven member into a plurality of divided areas and supplies different drive signals to the divided areas so as to implement a drive control.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 11, 2007
    Inventors: Haruo Onozuka, Tatsuo Saito, Katsuji Ozawa, Yukio Okazaki