Abstract: In the image processor system of the invention, an image processor and a plurality of image memories are connected through a plurality of image buses. The image processor and image memories are also connected through a control bus, as is a CPU. The image processor has a start signal output gate circuit. When the gate circuit is initiated by the CPU, it simultaneously outputs start signals designating image data output to the image buses designated by the CPU. Each image memory has a start signal input gate circuit and an output gate circuit. The start input gate circuit receives the start signal from the image bus designated by the CPU through the control bus. The output gate circuit starts image data output to the designated image bus in response to the start signal received at the start signal input gate circuit and in synchronism with the bus cycle of the image bus.

Abstract: An input/output start instruction includes, as parameters, a channel number, an input/output device number, a channel control block address and a termination que number. A channel receives the channel control block address and reads out the contents of the channel control block from a main memory and sets it in a service table in the channel whereby an input/output processing is executed.

Abstract: Disclosed is a memory control system for a data processing system in which the length of an access unit to a memory can be different from the lengths of information words which can be processed and which can include data, addresses, and instructions and operands processed in an arithmetic control apparatus, and combinations thereof. The disclosed memory control system provides an address boundary for effecting a read/write operation with respect to the memory of information words having a half-word length and a full-word length. The half-word length information words can correspond to 2n times a minimum word length, n being a positive integer, and the access unit length can be equal to the minimum unit word length. In a disclosed embodiment, the minimum unit word length and the access unit length can be an 8 bit byte. Thus, a half-word length can be 16 bits and a full-word length can be 32 bits.

Abstract: An information processing system having a main memory unit, an arithmetic control unit, and a plurality of input/output units, is comprised of a first bus, which is bidirectional, commonly connecting the main memory unit, the arithmetic control unit, and at least one input/output unit, a bus controller for controlling data transfer between two units connecting to the first bus, a second bus, which is also bidirectional, commonly connecting to the arithmetic control unit with at least another input/output unit, and a bus control means which is provided in the arithmetic control unit and controls data transfer between two units connecting to the second bus. The information processing system uses various units connecting to the first and second buses in time sharing and multiplexing mode.

Abstract: An address management system includes a central processing unit (CPU) and an address management unit arranged between a direct memory device (DMA) and a main memory unit to control memory access from the CPU and DMA. Segment registers for address expansion are provided in the CPU and DMA, respectively. The address management unit includes a conversion table for converting logical address data and segment data and segment data from the CPU and DMA into a corresponding physical address data, and the conversion table includes a bit position for detecting an address error and a control bit for selecting a memory access to a local memory or a shared memory.

Abstract: A microprogrammed computer comprises an instruction register for registering a machine instruction word; a decode read only memory (DROM) for storing the start address data of microprogram routines which correspond to machine instruction words, respectively, and the control bit data which correspond to the machine instruction words, respectively; and a read only memory (ROM) for storing a plurality of microprograms each consisting of microinstructions. The microprogrammed computer has such a hardware structure that each control bit datum in the DROM may serve to change the function of a microinstruction and the execution sequence of the microprograms in the ROM.