Abstract: Described is an error-correcting and error-detecting system including a check-bits generating circuit which is formed in accordance with a (k,l) type check matrix, such (k,l) type check matrix being formed from an (m,l) type reference sub-matrix (where m<k) and one or more (m,l) type sub-matrices, and each of the (m,l) type sub-matrices being derived from the (m,l) type reference sub-matrix by replacing unit-matrices of the (m,l) type reference sub-matrix with each other in accordance with a circular shift; wherein a desired check-bits code of an input data is obtained by multiplying the input data with respective reference sub-matrix and sub-matrices and by rearranging respective multiplied results produced from the respective rows of these reference sub-matrix and sub-matrices.

Abstract: A memory access control system is provided between one or more accessing devices and a main memory composed of a plurality of independently accessible logical storages, and receives a request from the accessing device and, based on the status of the main memory, permits access to one of the logical storages. The memory access control system comprises a shift register, composed of stages corresponding to the cycle time of the main memory, for storing address information sufficient for identifying a busy one of the logical storages and for sequentially shifting the stored content in synchronism with a clock signal, and a comparator circuit for comparing the content of each stage of the shift register with address information of the logical storage designated based on the request from the accessing device, receiving the request based on the result of the comparison, and generating a control signal for accessing the designated logical storage.