Abstract: A diagnosis method executed by a processor includes receiving signal data at a timing of a first clock signal; setting a diagnosis period to perform a diagnosis of a memory with a predetermined period; executing a write operation and a read operation of the signal data on the memory at a timing of a second clock signal that is higher in rate than the first clock signal within the diagnosis period; executing at least one of operations included in the diagnosis of the memory using diagnosis data at a timing of the second clock signal during a period responsive to a difference between a number of first clock pulses of the first clock signal within the diagnosis period and a number of second clock pulses of the second clock signal within the diagnosis period; and diagnosing the memory by repeating the diagnosis period by a plurality of times.

Abstract: A diagnosis method executed by a processor includes receiving signal data at a timing of a first clock signal; setting a diagnosis period to perform a diagnosis of a memory with a predetermined period; executing a write operation and a read operation of the signal data on the memory at a timing of a second clock signal that is higher in rate than the first clock signal within the diagnosis period; executing at least one of operations included in the diagnosis of the memory using diagnosis data at a timing of the second clock signal during a period responsive to a difference between a number of first clock pulses of the first clock signal within the diagnosis period and a number of second clock pulses of the second clock signal within the diagnosis period; and diagnosing the memory by repeating the diagnosis period by a plurality of times.

Abstract: A client interface unit receives a pause frame transmitted from a client device compatible with a relatively low communication rate. A data rate conversion unit generates a plurality of pause frames in accordance with a pause time designated by the received one pause frame and transmits the plurality of pause frames to a frame processing unit compatible with a relatively high communication rate. The frame processing unit stops transmitting a frame destined to the client device in accordance with the plurality of pause frames.

Abstract: A client interface unit receives a pause frame transmitted from a client device compatible with a relatively low communication rate. A data rate conversion unit generates a plurality of pause frames in accordance with a pause time designated by the received one pause frame and transmits the plurality of pause frames to a frame processing unit compatible with a relatively high communication rate. The frame processing unit stops transmitting a frame destined to the client device in accordance with the plurality of pause frames.

Abstract: A transmission device includes a temporary storage unit that is provided for each port receiving input data, stores the data temporarily, and outputs the temporarily stored data in response to a read enable signal, a storage unit that performs time-division multiplexing on the data output from the temporary storage unit in response to the read enable signal and stores the data, a flow monitoring unit that monitors a data flow for each of the ports, and a control unit that selects a temporary storage unit that is a read enable target from the temporary storage units corresponding to the ports to which the data is input, by a weighted round robin system in accordance with the data flow for each of the ports, and outputs the read enable signal to the selected temporary storage unit.

Abstract: A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.

Abstract: Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.

Abstract: A transmission device includes a temporary storage unit that is provided for each port receiving input data, stores the data temporarily, and outputs the temporarily stored data in response to a read enable signal, a storage unit that performs time-division multiplexing on the data output from the temporary storage unit in response to the read enable signal and stores the data, a flow monitoring unit that monitors a data flow for each of the ports, and a control unit that selects a temporary storage unit that is a read enable target from the temporary storage units corresponding to the ports to which the data is input, by a weighed round robin system in accordance with the data flow for each of the ports, and outputs the read enable signal to the selected temporary storage unit.

Abstract: A cross-connect system includes a mapping unit that maps second signal frames on which cross-connection is performed with a space switch, into third signal frames on which cross-connection is performed with the space switch and a time switch; a selection unit that selects either first signal frames on which cross-connection is performed with the space switch and the time switch and corresponding clock signals, or the third signal frames and corresponding clock signals; a cross-connection unit that receives either the first signal frames and corresponding clock signals or the third signal frames and corresponding clock signals selected by the selection unit and performs cross-connection for either the first signal frames or the third signal frames; and a demapping unit that demaps the third signal frames output from the cross-connection unit into the second signal frames and output the second signal frames.

Abstract: Each of a first switching processor and a second switching processor included in a switching device switches plural pieces of data to determined destinations. A controller bypass-transmits a determined number of pieces of data received by the first switching processor to the second switching processor according to a congestion state of the first switching processor to make both of the first switching processor and the second switching processor perform a switching process. Alternatively, the controller bypass-transmits a determined number of pieces of data received by the second switching processor to the first switching processor according to a congestion state of the second switching processor to make both of the first switching processor and the second switching processor perform a switching process.

Abstract: In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded.

Abstract: In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit.

Abstract: In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit.

Abstract: In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded.

Abstract: The invention relates to provide a cross-connect switch and a route monitoring assist apparatus both suitable for a synchronous transfer mode. An object of the invention is to attain cross-connect at a low cost with reliability in a much higher rate group than in the conventional example. To this end, the invention provides a cross-connect switch comprising a multiport storage section having a plurality of read ports randomly accessible and a plurality of write ports to which data of a plurality of channels that are time-division-multiplexed are input individually in parallel; an address storage section for storing addresses to be supplied to the respective read ports; and a controlling section for writing data in units of a plurality of channels by supplying write addresses sequentially to each of the write ports, and for supplying addresses stored in the address storage section to the respective read ports.

Abstract: A TSA circuit which receives as input upper side incoming transmission data from a super high speed ring network and lower side incoming transmission data from a high speed ring network and outputs upper side outgoing transmission data to the super high speed ring network and lower side outgoing transmission data to the high speed ring network, provided with a time slot assignment function block which has a time switch and a space switch and produces outgoing transmission data obtained by switching channels for the incoming transmission data in units of bits, whereby high speed and large volume incoming transmission data can be processed for time slot assignment (TSA), interchanged in channels, and sent out as outgoing transmission data by a relatively small sized circuit configuration.

Abstract: A time slot assignment circuit capable of performing channel setting with a high efficiency and with a high degree of freedom of channel setting with respect to a large volume of transmission data and in addition having a small circuit scale and low power consumption, provided a time switch provided with a transmission data memory into which transmission data is sequentially written and performing switching in a time domain with respect to the transmission data, a space switch for performing switching in a space domain with respect to an output thereof, an address control memory which outputs a channel setting address for controlling the two switches, and a channel setting information converting unit for converting a channel setting information from the outside to a channel setting address and an accessing address for the memory.

Abstract: A time-slot interchanger includes first and second time switches and a space switch installed between the first and second time switches. The first time switch includes a first part for supplying data, which is produced by adding a blank region to input data supplied to the first time switch, in n systems (n is an integer), in parallel to the space switch. And the second time switch includes a second part for supplying output data, which is produced by removing the blank region from data received in the n systems and in parallel from the space switch.

Abstract: A pulse insertion circuit alternately distributes serial input data at a predetermined data clocking rate into first and second parallel input data, which are synchronously and simultaneously written into and read from a memory, the second input data as read being delayed by one bit. A selection means selects between the second input data and the one-bit delayed second input data and further switches between and establishes either a direct or a cross connection between the selected one of the second input data, as read or as delayed, and the first input data and the first and second output terminals thereof, at which there are produced, correspondingly, parallel and selected, first and second input data.