Patents by Inventor Yukio Takano
Yukio Takano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20100004275Abstract: A medicament for suppressing development of tolerance to analgesic effect induced by administration of a narcotic analgesic such as morphine, which comprises an antagonist of the vasopressin receptor 1b as an active ingredient.Type: ApplicationFiled: June 8, 2009Publication date: January 7, 2010Applicants: KYOTO UNIVERSITY, FUKUOKA UNIVERSITY, JAPAN HEALTH SCIENCES FOUNDATIONInventors: Gozoh Tsujimoto, Yukio Takano, Kenji Honda, Akito Tanoue
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Publication number: 20080227802Abstract: A medicament for suppressing development of tolerance to analgesic effect induced by administration of a narcotic analgesic such as morphine, which comprises an antagonist of the vasopressin receptor 1b as an active ingredient.Type: ApplicationFiled: December 26, 2005Publication date: September 18, 2008Applicants: KYOTO UNIVERSITY, FUKUOKA UNIVERSITY, JAPAN HEALTH SCIENCES FOUNDATIONInventors: Gozoh Tsujimoto, Yukio Takano, Kenji Honda, Akito Tanoue
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Patent number: 6815741Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.Type: GrantFiled: July 23, 2003Date of Patent: November 9, 2004Assignee: Renesas Technology Corp.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Publication number: 20040124447Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.Type: ApplicationFiled: July 23, 2003Publication date: July 1, 2004Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 6733875Abstract: A porous member for pneumatic bearings or the like provides a controlled gas flow rate across a porous ceramic body, which can be readily achieved by a facilitated treatment. The porous body has its outer surface portion covered by a surface layer comprised of fine silica particles which are impregnated in the porous body. The surface layer is subjected to a heat treatment to form restricted passages which are in communication with, and smaller in size than pores within the porous body.Type: GrantFiled: November 9, 1994Date of Patent: May 11, 2004Assignee: Toto, Ltd.Inventors: Yukio Takano, Ryuichi Kojo, Takayuki Hirota
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Patent number: 6630697Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.Type: GrantFiled: July 25, 2001Date of Patent: October 7, 2003Assignee: Hitachi, Ltd.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Publication number: 20010045621Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer si reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.Type: ApplicationFiled: July 25, 2001Publication date: November 29, 2001Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 6297523Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5 and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the GaAs single crystal can be made uniform.Type: GrantFiled: August 18, 1993Date of Patent: October 2, 2001Assignee: Hitachi, Ltd.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 6294804Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.Type: GrantFiled: October 3, 1997Date of Patent: September 25, 2001Assignee: Hitachi, Ltd.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 5770873Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and the minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent material (substrate) is the GaAs single crystal can be made uniform.Type: GrantFiled: June 1, 1995Date of Patent: June 23, 1998Assignee: Hitachi, Ltd.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 5733805Abstract: By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4.times.10.sup.-5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1.times.10.sup.16 cm.sup.-3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.Type: GrantFiled: June 1, 1995Date of Patent: March 31, 1998Assignee: Hitachi, Ltd.Inventors: Yoshihisa Fujisaki, Yukio Takano, Tsutomu Ishiba
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Patent number: 4977307Abstract: An apparatus for heating a sample within a vacuum chamber according to the present invention includes a preliminary exhaust chamber connected with a vacuum chamber of an analyzer and the like through a gate valve. A sample stage is disposed within the vacuum chamber, and a sample holder is detachably disposed on this stage. The preliminary exhaust chamber is provided with a transfer device for transferring the sample holder between the preliminary exhaust chamber and the vacuum chamber to mount the sample holder on the stage and detach the sample holder from the stage. The sample holder is provided with a heater and a temperature-measuring element mounted thereon, the heater and temperature-measuring element being connected with the respective connectors mounted on the sample holder. A fixed connector is connected with the connectors when the sample holder is mounted on the stage by means of the transfer device.Type: GrantFiled: January 17, 1989Date of Patent: December 11, 1990Assignee: Horiba, Ltd.Inventors: Yoshihiko Motoi, Naoki Yamamoto, Yukio Takano
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Patent number: 4916720Abstract: An X-ray analyzer for performing both X-ray fluorescence and X-ray diffraction analysis is provided with an X-ray source, an X-ray guide tube for collimating X-rays from the source, a vacuum tank in which the guide tube is partially disposed, a rotatable sample table for holding a sample adjacent the guide tube, and an X-ray detector movable away from and towards the sample table, and also rotatable independently of the sample table.Type: GrantFiled: November 15, 1988Date of Patent: April 10, 1990Assignees: Horiba, Ltd., Hitachi, Ltd.Inventors: Naoki Yamamoto, Yukio Takano, Yoshinori Hosokawa, Kenji Yoshino
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Patent number: 4837137Abstract: In the photoreceptor described in the specification, an electroconductive base has an amorphous silicon type photoconductive layer coated over a blocking layer on the base and an amorphous carbon-containing surface layer, coated over a buffer layer on the photoconductive layer, has a hardness on the free surface side which is higher than the hardness on the buffer surface side. Apparatus for preparing the photoreceptor includes a CVD vacuum chamber and an arrangement for supplying selected layer-forming gases to the chamber in a controlled manner.Type: GrantFiled: December 2, 1987Date of Patent: June 6, 1989Assignee: Fuji Electric Co., Ltd.Inventors: Koichi Aizawa, Toyoki Kazama, Yukio Takano, Yukihisa Tamura
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Patent number: 4833055Abstract: An electrophotographic photoreceptor comprises a conductive base, a photoconductive layer formed of amophous silicon on the conductive base, a buffer layer on the photoconductive layer, and a surface layer covering the photoconductive layer through the buffer layer, wherein the buffer layer is formed of amorphous carbon.Type: GrantFiled: June 4, 1987Date of Patent: May 23, 1989Assignee: Fuji Electric Co., Ltd.Inventors: Toyoki Kazama, Koichi Aizawa, Kenichi Hara, Toshiyuki Iijima, Yukio Takano
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Patent number: 4770966Abstract: A photosensitive material comprising a photosensitive layer composed of an amorphous silicon-based material formed on an electrically conductive support, and a surface layer formed on said photosensitive layer, the surface layer being composed of amorphous carbon containing hydrogen and fluorine has improved printing durability and humidity resistance.Type: GrantFiled: March 12, 1987Date of Patent: September 13, 1988Assignee: Fuji Electric Co., Ltd.Inventors: Toyoki Kazama, Koichi Aizawa, Kenichi Hara, Toshiyuki Iijima, Yukio Takano
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Patent number: 4276114Abstract: This invention relates to a semiconductor substrate and a method of manufacturing the same. In a semiconductor manufacturing process for a Si single crystal wafer or the like, before the step of mirror polishing, the rear surface of a Si wafer is ground to form a damaged layer having a certain fixed thickness, the Si wafer is subsequently etched by chemical etching if desired, and the rear surface is further formed with an oxide film by thermal oxidation if desired, whereby a semiconductor substrate exhibiting an intense gettering effect is manufactured.Type: GrantFiled: February 6, 1979Date of Patent: June 30, 1981Assignee: Hitachi, Ltd.Inventors: Yukio Takano, Masahiko Ogirima, Shigeru Aoki, Michiyoshi Maki, Shigeo Kato