Patents by Inventor Yukio Tani
Yukio Tani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8640943Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: GrantFiled: September 10, 2012Date of Patent: February 4, 2014Assignee: Renesas Electronics CorporationInventors: Hiroshi Maki, Yukio Tani
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Patent number: 8574463Abstract: A metal complex dye, containing a ligand LL1 having a structure represented by Formula (I): wherein R1 and R2 represent a specific substituent; L1 and L2 represent a group composed of at least one kind of group selected from the group consisting of an ethenylene group, an ethynylene group and an arylene group, and conjugate with R1 or R2, and the bipyridine; the ethenylene group and the arylene group may be substituted or unsubstituted; R3 and R4 represent a substituent; n1 and n2 represent an integer of 0 to 3; A1 and A2 represent an acidic group or a salt thereof; and n3 and n4 represent an integer of 0 to 3.Type: GrantFiled: November 29, 2012Date of Patent: November 5, 2013Assignee: FUJIFILM CorporationInventors: Yukio Tani, Tatsuya Susuki, Katsumi Kobayashi, Keizo Kimura
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Publication number: 20130068826Abstract: A die bonder includes a die supply stage, which is configured to hold a wafer; a first head having a first collet, which is configured to pick up a die from the wafer and to attach the die, provisionally, on a target to be conducted with mounting thereon, on the attach stage; a second head having a second collet, which is configured to conduct main compression of the die, which is provisionally attached on the attach stage, on the target to be conducted with mounting; and a controller apparatus, wherein the controller apparatus controls the first head to pick up a next die from the die supply stage, during when the second head conducts the main compression on the die onto the target to be conducted with mounting, thereby achieving the die bonder and the die bonding method being stable in quality.Type: ApplicationFiled: March 9, 2012Publication date: March 21, 2013Applicant: Hitachi High-Tech Instruments Co., Ltd.Inventors: Hiroshi Maki, Masayuki Mochizuki, Yukio Tani, Takehito Mochizuki
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Publication number: 20130068824Abstract: A bonding method of a die bonder with a single conveyance lane and a single bonding head, or a plurality of conveyance lanes and a plurality of bonding heads includes the steps of generating a classification map of class dies with different electric properties on the wafer, which are classified in accordance with a plurality of grades, picking up the die from the wafer, bonding the die onto a substrate or the die using a bonding head, conveying a class substrate corresponding to the class die on the conveyance lane in a unit of the class substrate, and further bonding the class die to the corresponding class substrate based on the classification map.Type: ApplicationFiled: August 15, 2012Publication date: March 21, 2013Applicant: Hitachi High-Tech Instruments Co., Ltd.Inventors: Masayuki MOCHIZUKI, Hiroshi Maki, Yukio Tani, Takehito Mochizuki
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Publication number: 20130068823Abstract: A die bonder and a bonding method are disclosed which make it possible to provide high-quality products, particularly even if a die is rotated through predetermined degrees relative to an already-bonded die and then laminated. In the die bonder and bonding method in which a die is picked up from a wafer by a pick-up head which then places the die on an alignment stage, and the die is picked up from the alignment stage by a bonding head which then bond the die onto a substrate or an already-bonded die, a posture of the die is rotated through predetermined degrees on a plane parallel to a plane on which the bonding is performed, before the bonding head picks up the die from the alignment stage.Type: ApplicationFiled: March 6, 2012Publication date: March 21, 2013Applicant: Hitachi High-Tech Instruments Co., Ltd.Inventors: Hiroshi MAKI, Masayuki MOCHIZUKI, Yukio TANI, Takehito MOCHIZUKI
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Publication number: 20120329211Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: ApplicationFiled: September 10, 2012Publication date: December 27, 2012Inventors: Hiroshi MAKI, Yukio TANI
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Patent number: 8292159Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: GrantFiled: November 14, 2011Date of Patent: October 23, 2012Assignees: Renesas Eletronics Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Hiroshi Maki, Yukio Tani
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Publication number: 20120058603Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: ApplicationFiled: November 14, 2011Publication date: March 8, 2012Inventors: Hiroshi MAKI, Yukio Tani
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Patent number: 8074868Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: GrantFiled: November 30, 2010Date of Patent: December 13, 2011Assignees: Renesas Electronics Corporation, Renesas Eastern Japan Semiconductor, Inc.Inventors: Hiroshi Maki, Yukio Tani
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Publication number: 20110213144Abstract: A dye, having a structure represented by formula (1A): wherein A represents a group of atoms necessary for forming a ring together with the carbon-nitrogen bond; at least one of Y1A and Y2A represents an acidic group, in which when they each represent an acidic group, they may be the same as or different from each other, or when only one of them represents an acidic group, the other represents an electron-withdrawing group; D represents a group to give a dye; n represents an integer of 1 or greater; L represents a single bond or a divalent linking group; and Y3A represents an acidic group.Type: ApplicationFiled: October 29, 2009Publication date: September 1, 2011Applicant: FUJIFILM CORPORATIONInventors: Katsumi Kobayashi, Keizo Kimura, Tatsuya Susuki, Hirotaka Satou, Yukio Tani
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Publication number: 20110076539Abstract: A method of producing a photoelectric conversion element, which the element contains an electrically conductive support, a photosensitive layer having porous semiconductor fine particles, a charge transfer layer; and a counter electrode, includes the steps of: applying a semiconductor dispersion liquid, in which the content of solids excluding semiconductor fine particles is 10% by mass or less based on the total amount of the dispersion liquid, on the support, to form a coating; heating the coating, to obtain porous semiconductor fine particles; and sensitizing the porous particles by adsorption of the following dye: wherein A represents a group of atoms necessary for forming a ring; at least one of Y1 and Y2 represents an acidic group and the other represents an electron-attracting group; D represents a dye residue; n represents 1 or a greater integer; L represents a single bond or divalent linking group; and Y3 represents an acidic group.Type: ApplicationFiled: September 23, 2010Publication date: March 31, 2011Applicant: FUJIFILM CorporationInventors: Katsumi KOBAYASHI, Yukio TANI, Keizo KIMURA
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Publication number: 20110070696Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: ApplicationFiled: November 30, 2010Publication date: March 24, 2011Inventors: Hiroshi Maki, Yukio Tani
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Patent number: 7861912Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: GrantFiled: July 14, 2010Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventors: Hiroshi Maki, Yukio Tani
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Publication number: 20100279464Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: ApplicationFiled: July 14, 2010Publication date: November 4, 2010Inventors: Hiroshi MAKI, Yukio Tani
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Patent number: 7757930Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: GrantFiled: August 10, 2007Date of Patent: July 20, 2010Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.Inventors: Hiroshi Maki, Yukio Tani
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Patent number: 7624612Abstract: An angle adjuster for a golf club shaft includes a pressing part that can advance and retreat towards and away from a space between two pressing force receiving parts. The pressing force receiving parts include grooves configured to receive a golf club shaft. When the pressing part is advanced against the golf club shaft, a bending force is applied to the shaft at a bending location on the shaft that lies between the pressing force receiving parts. This occurs while the shaft is received in, the receiving grooves of the pressing force receiving parts.Type: GrantFiled: November 20, 2007Date of Patent: December 1, 2009Assignee: Japana Co., Ltd.Inventors: Haruhisa Toda, Yukio Tani, Katsunori Yoshida
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Publication number: 20080202193Abstract: An angle adjuster for a golf club shaft includes a pressing part that can advance and retreat towards and away from a space between two pressing force receiving parts. The pressing force receiving parts include grooves configured to receive a golf club shaft. When the pressing part is advanced against the golf club shaft, a bending force is applied to the shaft at a bending location on the shaft that lies between the pressing force receiving parts. This occurs while the shaft is received in, the receiving grooves of the pressing force receiving parts.Type: ApplicationFiled: November 20, 2007Publication date: August 28, 2008Inventors: Haruhisa Toda, Yukio Tani, Katsunori Yoshida
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Publication number: 20070287262Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, then the matrix substrate is disposed above the semiconductor chips on the first heating stage, subsequently the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding while heating the chips directly by the first heating stage, thereafter the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then on the second heating stage the semiconductor chips are thermocompression-bonded to the matrix substrate while being heated directly by the second heating stage.Type: ApplicationFiled: August 10, 2007Publication date: December 13, 2007Inventors: Hiroshi MAKI, Yukio Tani
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Patent number: 7270258Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, and then the matrix substrate is disposed above the semiconductor chips on the first heating stage. Subsequently, the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding, while heating the chips directly by the first heating stage. Thereafter, the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then, on the second heating stage, the semiconductor chips are thermocompression-bonded to the matrix substrate, while being heated directly by the second heating stage.Type: GrantFiled: July 30, 2004Date of Patent: September 18, 2007Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor, Inc.Inventors: Hiroshi Maki, Yukio Tani
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Publication number: 20050061856Abstract: Productivity is to be improved in assembling a semiconductor integrated circuit device. A matrix substrate is provided and semiconductor chips are disposed on a first heating stage, and then the matrix substrate is disposed above the semiconductor chips on the first heating stage. Subsequently, the semiconductor chips and the matrix substrate are bonded to each other temporarily by thermocompression bonding, while heating the chips directly by the first heating stage. Thereafter, the temporarily bonded matrix substrate is disposed on a second heating stage adjacent to the first heating stage, and then, on the second heating stages, the semiconductor chips are thermocompression-bonded to the matrix substrate, while being heated directly by the second heating stage.Type: ApplicationFiled: July 30, 2004Publication date: March 24, 2005Inventors: Hiroshi Maki, Yukio Tani