Abstract: The labelling circuit of this invention comprises first and second table memories, which designate when pixels assigned with different label values are of the same linked components and whose contents are updated based on linked information produced by a label extracting circuit. The labelling circuit further comprises first through third selectors. The first and second selectors select the label value of an intermediate processed image previously produced by the label extracting circuit, or one of label values of new linked information produced by the label extracting circuit, as an address for the first and second table memories. The third selector selects one of output data of the first and second table memories as output image data.

Abstract: An image processing apparatus including an affine conversion address generator, an image read memory, and an image write memory are connected via a control bus. The image read and write memories are connected via an image bus which operates independently of the control bus. Image data, which is designated by an affine conversion address output from the affine conversion address generator onto the control bus, is read out from the image read memory. The read image data is then transferred to the image write memory together with a busy signal indicating data transfer via the image bus. The image write memory stores the transferred image data in accordance with raster addresses sequentially generated therein.

Abstract: An affine conversion address generated by an affine conversion address generator and a detection signal from an outside-the-image memory area detector are transferred to a first image memory, together with a read signal, via a control bus. Image data is read out from a pixel position of the first image memory designated by the affine conversion address on the address bus of the control bus. The image data read out from the first image memory is supplied to a gate circuit together with the detection signal on the control bus. The gate circuit outputs the image data read out from the first image memory directly or after converting it to predetermined image data in accordance with the detection signal on the control bus. The image data output from the gate circuit is transferred to a second image memory, together with a busy signal indicating a data transfer, via an image bus provided independently of the control bus.

Abstract: In the image processor system of the invention, an image processor and a plurality of image memories are connected through a plurality of image buses. The image processor and image memories are also connected through a control bus, as is a CPU. The image processor has a start signal output gate circuit. When the gate circuit is initiated by the CPU, it simultaneously outputs start signals designating image data output to the image buses designated by the CPU. Each image memory has a start signal input gate circuit and an output gate circuit. The start input gate circuit receives the start signal from the image bus designated by the CPU through the control bus. The output gate circuit starts image data output to the designated image bus in response to the start signal received at the start signal input gate circuit and in synchronism with the bus cycle of the image bus.

Abstract: A linked component extraction circuit has a FIFO memory for sequentially storing information pairs each consisting of two label values which are generated from a linked component detector and which have a linking relationship therebetween, and for reading out a currently oldest information pair when the FIFO memory is subjected to read access. A read/write unit reads out storage data (i.e., the label value) from a memory area of the table memory at an address accessed by the first label value of the information pair or the readout output data and writes the second label value of the information pair read out from the FIFO memory at the same address. The storage data read out from the table memory at the address accessed by the first label value is compared with the first label value by a comparator to generate a coincidence or noncoincidence signal.

Abstract: A digital input apparatus is provided which is used as an input apparatus for a digital signal processor and can eliminate noise components resulting from electromagnetic induction and resulting from chattering which is produced by the opening or closing of a contact. One input signal outputted from the multiplexer (105) is applied through a latch flip-flop (108) to a counter (114) used on a time sharing basis so that counting is effected. Individual counts corresponding to a plurality of input signals are stored in a memory (117). When a count becomes all "1's" or "0's", the counter (114) produces a carry signal or a borrow signal supplied to a J-K flip-flop (113). The J-K flip-flop (113) produces an input signal of a predetermined waveform free from noise components.