Abstract: An image data processing apparatus includes: plural arithmetic processing sections; a main memory; and a cache memory, wherein slices of the image data are sequentially and cyclically assigned to the plural arithmetic processing sections and plural slices to be processed are set as objects of processing, respectively, and the plural arithmetic processing sections process the image data in parallel to establish a consistent relationship of the processing of each slice with processing of the immediately preceding slice, in which the current slice and the immediately preceding slice can be simultaneously processed in parallel so that a reference macroblock of the macroblock in processing in the current slice may partly overlap with a reference macroblock of the macroblock in processing in the immediately preceding slice.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently. The apparatus includes a plurality of macro block processing sections for coding moving picture data concurrently on a macro block by macro block basis, and a state management section for managing the state of processing of each macro block in a single picture. The state management section being adapted to manage each macro block in a single picture in terms of being in a process completed state.

Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently macro blocks. The apparatus includes a plurality of macro block processing sections for coding moving picture data concurrently on a macro block by macro block basis, each macro block processing section being adapted to select a position or a region out of a plurality of regions produced by dividing a picture by a predetermined number of rows, detect a processable macro block by sequentially retrieving the macro blocks of the selected region according to a predetermined scanning sequence and code the detected processable macro block.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: An image data processing apparatus includes: plural arithmetic processing sections; a main memory; and a cache memory, wherein slices of the image data are sequentially and cyclically assigned to the plural arithmetic processing sections and plural slices to be processed are set as objects of processing, respectively, and the plural arithmetic processing sections process the image data in parallel to establish a consistent relationship of the processing of each slice with processing of the immediately preceding slice, in which the current slice and the immediately preceding slice can be simultaneously processed in parallel so that a reference macroblock of the macroblock in processing in the current slice may partly overlap with a reference macroblock of the macroblock in processing in the immediately preceding slice.

Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently according to a new standard such as the MPEG-4 Standard or the H. 264/MPEG-4AVC Standard.

Abstract: A coding apparatus that can have a plurality of macro blocks processed concurrently according to a new standard such as the MPEG-4 Standard or the H. 264/MPEG-4AVC Standard.

Abstract: A semiconductor device has a plurality of first pads to a plurality of fourth pads laid out in a first direction, thereby forming first to fourth pad rows. The first to fourth pad rows are laid out in the named order in a second direction orthogonal to the first direction. First to fourth leads are respectively connected between the first to fourth pad rows and a semiconductor chip. A first slanted side inclined to the first direction is formed at each second pad at that corner which lies on that side of the third pad row. A second slanted side inclined to the second direction in such a way as to face the first slanted side is formed at each third pad. Each first lead has a first slanted portion provided between the first slanted side and the second slanted side and extending in a direction oblique to the first direction.

Abstract: An image processing apparatus able to encode and decode images by a low cost, small sized circuit configuration, having a temporary storage portion for temporarily storing data, an encoding/decoding processing portion for reading and writing data successively with respect to the temporary storage portion and encoding and decoding the image data in parallel, and a storage control portion for controlling the read and write operations of the data with respect to the temporary storage portion, wherein the storage control portion controls the read and write operations with respect to the temporary storage portion by the encoding/decoding processing portion in the encoding processing and at least read and write operations to the temporary storage portion by the encoding/decoding processing portion in the decoding processing so as to be performed within one frame's worth or one field's worth of processing period in a time division manner.

Abstract: A semiconductor device has a plurality of first pads to a plurality of fourth pads laid out in a first direction, thereby forming first to fourth pad rows. The first to fourth pad rows are laid out in the named order in a second direction orthogonal to the first direction. First to fourth leads are respectively connected between the first to fourth pad rows and a semiconductor chip. A first slanted side inclined to the first direction is formed at each second pad at that corner which lies on that side of the third pad row. A second slanted side inclined to the second direction in such a way as to face the first slanted side is formed at each third pad. Each first lead has a first slanted portion provided between the first slanted side and the second slanted side and extending in a direction oblique to the first direction.

Abstract: A motion detecting and motion compensative prediction circuit includes an integer pixel accuracy calculating unit for carrying out calculation for detecting, with an integer pixel accuracy, a portion most approximate to an object of a current frame from a predetermined reference frame, and a half pixel accuracy calculating and motion compensative prediction unit (including a buffer memory, a re-arranging unit for rearranging a picture data supplied thereto through the buffer memory by a pixel unit, and an interpolation unit for subjecting the picture data re-arranged by the re-arranging unit to linear interpolation calculation).