Abstract: In one embodiment, a multiplex control device includes three or more control modules to execute same operations for same input signals, and a majority decision module to output an output signal that matches majority of output signals outputted by the control modules. Each control module includes an input module to convert an input signal into an input value, a first determination module to obtain input values from input modules of respective control modules to determine whether majority of input values among the obtained input values match, an operation executing module to execute an operation using the matched input value to generate an output value, a second determination module to obtain output values from operation executing modules of respective control modules to determine whether majority of output values among the obtained output values match, and an output module to convert the matched output value to generate an output signal.

Abstract: In one embodiment, a multiplex control apparatus includes first to Nth input modules to convert input signals to input values, where N is an integer of three or more, and first to Nth operation modules to operate the input values to generate output values. The apparatus further includes first to Nth output modules to convert the output values to output signals outputted to a majority decision module, and first to Nth power supply modules to supply power to the first to Nth input, operation and output modules, respectively. An Xth output module is configured so that an output signal line between the Xth output module and the majority decision module is placed in an open state that is a safe-side status, if power supply from an Xth power supply module to the Xth output module is at a stop, where X is an integer from 1 to N.

Abstract: In one embodiment, a multiplex control device includes three or more control modules to execute same operations for same input signals, and a majority decision module to output an output signal that matches majority of output signals outputted by the control modules. Each control module includes an input module to convert an input signal into an input value, a first determination module to obtain input values from input modules of respective control modules to determine whether majority of input values among the obtained input values match, an operation executing module to execute an operation using the matched input value to generate an output value, a second determination module to obtain output values from operation executing modules of respective control modules to determine whether majority of output values among the obtained output values match, and an output module to convert the matched output value to generate an output signal.

Abstract: Provided are: a programmable logic device capable of efficiently verifying whether an internal status of each sequential circuit makes transition equivalent to that of a logic program written in a hardware description language (HDL); and a verification method for the programmable logic device. A programmable logic device 10 includes: an I/O unit 17 that inputs and outputs digital signals to and from implemented logic elements and an outside; generation units 12 (12a, 12b, 12c, 12d) that acquire internal status signals of sequential circuits included in respective corresponding divided regions 11 (11a, 11b, 11c, 11d) to each of which a group of the logic elements is assigned, and generate status information 13 (13a, 13b, 13c, 13d) for each divided region 11 as a unit; and a selective output unit 14 that acquires the status information 13 from each divided region 11 and selectively outputs the status information 13 to the outside.

Abstract: Provided is a programmable control apparatus for performing a self-diagnosis process using a short-period single loop. The programmable control apparatus includes: a signal processing unit configured to sequentially process inputted external signals based on a program in a memory; a data acquisition unit configured to acquire data from a specified nth block of a plurality of blocks obtained by dividing an area of the memory; a diagnostic unit configured to diagnose health of the nth block based on the acquired data and then prompt a next external signal to be processed; and a block specification unit configured to cause health of an (n+1)th block to be diagnosed after the next external signal is processed.

Abstract: In a digital control device, when a normal mode for carrying out a normal process is selected by a mode switch, a computation unit transfers base process code and APL process code which controls the normal process from a code storage device to a main memory, loads the base process code and the APL process code which are transferred to the main memory, and carries out the normal process. When a test mode for carrying out a test process is selected by the mode switch, the computation unit transfers the base process code and test process code which controls the test process from the code storage device to the main memory, loads the base process code and the test process code which are transferred to the main memory, and carries out the test process.

Abstract: According to an embodiment, a control system has: a logic module substrate that has a logic FPGA on which logic is mounted, a transmission module that transmits an output logic state signal, which is logic state signal representing an interim logic state of a process by the logic FPGA of deriving a logic output signal from the logic input signals, and a logic monitoring device that displays to monitor the logic state signal transmitted from the transmission module. The logic module substrate includes an event detection unit that detects a change in the logic state signal. Only when a change in the logic state signals is detected by the event detection unit, the logic output state signal being transmitted to the transmission module.

Abstract: According to an embodiment, a control system has: a logic module substrate that has a logic FPGA on which logic is mounted, a transmission module that transmits an output logic state signal, which is logic state signal representing an interim logic state of a process by the logic FPGA of deriving a logic output signal from the logic input signals, and a logic monitoring device that displays to monitor the logic state signal transmitted from the transmission module. The logic module substrate includes an event detection unit that detects a change in the logic state signal. Only when a change in the logic state signals is detected by the event detection unit, the logic output state signal being transmitted to the transmission module.

Abstract: A control device includes: memory diagnosis means for setting a power-on status when an electric power is turned on and diagnosing an ECC memory; restarting means for restarting the control device when the memory diagnosis means detects a correctable error of the ECC memory during the power-on status of the ECC memory; and operation processing means for resetting the power-on status and performing a normal operation when the memory diagnosis means does not detect a correctable error of the ECC memory, while performing the normal operation when a correctable error of the ECC memory is detected because of the restart of the control device by soft reset after the reset of the power-on status but when the control device is not in the power-on status.

Abstract: A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.

Abstract: A control device includes: memory diagnosis means for setting a power-on status when an electric power is turned on and diagnosing an ECC memory; restarting means for restarting the control device when the memory diagnosis means detects a correctable error of the ECC memory during the power-on status of the ECC memory; and operation processing means for resetting the power-on status and performing a normal operation when the memory diagnosis means does not detect a correctable error of the ECC memory, while performing the normal operation when a correctable error of the ECC memory is detected because of the restart of the control device by soft reset after the reset of the power-on status but when the control device is not in the power-on status.

Abstract: A memory control unit controls writing and reading of data to the slave device according to an instruction from the master device. A bus diagnosis line is directly connected from the bus signal control circuit to a bus signal receiving terminal of the slave device without passing through the address bus and the control signal line. A bus signal abnormality processing unit compares an output bus signal output from the bus signal control circuit to the address bus and the control signal line with a feedback bus signal fed back through the bus diagnosis line to determine the presence/absence of a difference. The memory control unit elongates a bus cycle period of a bus cycle of operation being executed when it is determined in the bus signal abnormality processing unit that the difference is present.