Patents by Inventor Yukitoshi Ota
Yukitoshi Ota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9474179Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.Type: GrantFiled: August 7, 2015Date of Patent: October 18, 2016Assignee: PANASONIC CORPORATIONInventors: Yukitoshi Ota, Fumito Itou, Kiyomi Hagihara
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Publication number: 20150359119Abstract: Provided is an electronic component package that does not lower reliability while enabling miniaturization and high performance of the electronic component package. The electronic component package includes a main substrate, a first electronic component provided on a main surface of the main substrate, a frame body disposed so as to face the main surface of the main substrate, and a first connection terminal and a second connection terminal disposed on the main surface of the main substrate along a first side of the frame body. The second connection terminal is disposed on the first side of the frame body at a position facing a vicinity of a midpoint of a side of the first electronic component, and the second connection terminal has an area larger than an area of the first connection terminal.Type: ApplicationFiled: August 7, 2015Publication date: December 10, 2015Inventors: YUKITOSHI OTA, FUMITO ITOU, KIYOMI HAGIHARA
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Patent number: 8736067Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.Type: GrantFiled: July 27, 2011Date of Patent: May 27, 2014Assignee: Panasonic CorporationInventors: Hiroshige Hirano, Yukitoshi Ota, Yutaka Itoh
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Patent number: 8710667Abstract: A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.Type: GrantFiled: November 4, 2011Date of Patent: April 29, 2014Assignee: Panasonic CorporationInventors: Hiroshige Hirano, Yukitoshi Ota
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Patent number: 8421236Abstract: A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.Type: GrantFiled: December 22, 2010Date of Patent: April 16, 2013Assignee: Panasonic CorporationInventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou
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Patent number: 8344515Abstract: A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.Type: GrantFiled: May 18, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Taichi Nishio, Hiroshige Hirano, Yukitoshi Ota
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Patent number: 8338958Abstract: A semiconductor device includes: a semiconductor substrate having a first surface as a surface on which an element is formed, and a second surface opposite to the first surface; a through hole formed so as to extend through the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through hole; and a conductive portion formed in a space surrounded by the insulating film in the through hole. The insulating film continuously extends on the inner wall of the through hole and on the second surface.Type: GrantFiled: July 26, 2010Date of Patent: December 25, 2012Assignee: Panasonic CorporationInventors: Taichi Nishio, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20120256322Abstract: A semiconductor device includes a first semiconductor chip provided with a first semiconductor element including a plurality of element electrodes; and a first substrate having an element mounting surface on which the first semiconductor chip is mounted. The first substrate includes a plurality of first electrodes, each formed on the element mounting surface; a plurality of first interconnects connected to the first electrodes; a plurality of second electrodes formed on a surface opposite to the element mounting surface; a plurality of second interconnects connected to the second electrodes; a plurality of through-hole interconnects penetrating the first substrate and connecting the first interconnects to the second interconnects; and a third semiconductor element. The first side of the first substrate is shorter than the first side of the first semiconductor chip.Type: ApplicationFiled: June 13, 2012Publication date: October 11, 2012Applicant: PANASONIC CORPORATIONInventors: Fumito Itou, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20120112354Abstract: A semiconductor device includes a first interconnect layer and a second interconnect layer provided above or under the first interconnect layer. The first interconnect layer includes a plurality of first interconnect blocks, and in each of the first interconnect blocks, a first interconnect has a first potential, and extends in at least two or more directions, and a second interconnect has a second potential, and extends in at least two or more directions. The second interconnect layer includes a third interconnect which electrically connects the first interconnect of one of a pair of adjacent first interconnect blocks and the first interconnect of the other of the pair of adjacent first interconnect blocks, and a fourth interconnect which electrically connects the second interconnect of one of the pair of adjacent first interconnect blocks and the second interconnect of the other of the pair of adjacent first interconnect blocks.Type: ApplicationFiled: November 4, 2011Publication date: May 10, 2012Applicant: PANASONIC CORPORATIONInventors: Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20120025394Abstract: A semiconductor device includes: a first insulating film formed on a substrate; a pad embedded in the first insulating film; and a second insulating film that is formed on the first insulating film and has an opening exposing at least part of the pad. The pad includes a plurality of pad interconnects, and an interconnect link is provided to electrically connect adjacent interconnects among the plurality of pad interconnects. The width of the pad interconnects is smaller than the height of the pad interconnects and larger than the width of the interconnect link.Type: ApplicationFiled: July 27, 2011Publication date: February 2, 2012Inventors: Hiroshige Hirano, Yukitoshi Ota, Yutaka Itoh
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Patent number: 8044482Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.Type: GrantFiled: August 12, 2009Date of Patent: October 25, 2011Assignee: Panasonic CorporationInventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
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Publication number: 20110175232Abstract: A semiconductor device includes an electrode pad formed above a semiconductor substrate, and being a connecting portion for an external electrical connection; a multilayer body including a plurality of first interconnect layers formed in a plurality of insulating films stacked between the semiconductor substrate and the connecting portion and including an upper interconnect connected to the connecting portion, and a via configured to connect the first interconnect layers; a ring body formed in the plurality of insulating films to surround the multilayer body without interposing space, and including a plurality of second interconnect layers and at least one line via linearly connecting the second interconnect layers; and a lead line electrically connecting the connecting portion to an internal circuit. The multilayer body is connected to the ring body by at least one of the plurality of first interconnect layers. The lead line is connected to the ring body.Type: ApplicationFiled: December 22, 2010Publication date: July 21, 2011Inventors: Yukitoshi OTA, Hiroshige Hirano, Yutaka Itou
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Publication number: 20100283130Abstract: A semiconductor device includes: a semiconductor substrate having a first surface as a surface on which an element is formed, and a second surface opposite to the first surface; a through hole formed so as to extend through the semiconductor substrate from the first surface to the second surface; an insulating film formed on an inner wall of the through hole; and a conductive portion formed in a space surrounded by the insulating film in the through hole. The insulating film continuously extends on the inner wall of the through hole and on the second surface.Type: ApplicationFiled: July 26, 2010Publication date: November 11, 2010Applicant: PANASONIC CORPORATIONInventors: Taichi NISHIO, Hiroshige Hirano, Yukitoshi Ota
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Publication number: 20100225005Abstract: A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.Type: ApplicationFiled: May 18, 2010Publication date: September 9, 2010Applicant: PANASONIC CORPORATIONInventors: Taichi NISHIO, Hiroshige Hirano, Yukitoshi Ota
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Patent number: 7777304Abstract: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.Type: GrantFiled: August 3, 2006Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Tsuyoshi Hamatani, Yukitoshi Ota
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Patent number: 7728429Abstract: A semiconductor device in accordance with the present invention includes IC chips (semiconductor elements) (2, 3, 4) having solder bumps (24) (projecting electrodes) formed on electrode pads, and a first wiring board (1) having connection terminals (7) to which the respective solder bumps (24) of the IC chips (2, 3, 4) are connected, external connection terminals (8) for connection to an external apparatus, and conductor wires (9) provided in respective groove portions formed in a board surface and connected to the respective connection terminals (7). In spite of the reduced pitch of the conductor wires (9), the presence of the groove portions enables an increase in cross section, allowing a reduction in wiring resistance.Type: GrantFiled: July 17, 2007Date of Patent: June 1, 2010Assignee: Panasonic CorporationInventors: Isamu Aokura, Toshiyuki Fukuda, Yukitoshi Ota, Keiji Miki
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Publication number: 20100090344Abstract: A semiconductor device includes an insulating film formed on a semiconductor substrate, a contact wiring formed in the insulating film, a protective film formed on the contact wiring and the insulating film, an opening portion formed in the protective film, the contact wiring being exposed through the opening portion, and an electrode pad formed in the opening portion, the electrode pad being electrically connected to the contact wiring. A region where the contact wiring is not provided is present below the opening portion.Type: ApplicationFiled: August 12, 2009Publication date: April 15, 2010Inventors: Yukitoshi Ota, Hiroshige Hirano, Yutaka Itou, Koji Koike
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Publication number: 20080087993Abstract: A semiconductor device in accordance with the present invention includes IC chips (semiconductor elements) (2, 3, 4) having solder bumps (24) (projecting electrodes) formed on electrode pads, and a first wiring board (1) having connection terminals (7) to which the respective solder bumps (24) of the IC chips (2, 3, 4) are connected, external connection terminals (8) for connection to an external apparatus, and conductor wires (9) provided in respective groove portions formed in a board surface and connected to the respective connection terminals (7). In spite of the reduced pitch of the conductor wires (9), the presence of the groove portions enables an increase in cross section, allowing a reduction in wiring resistance.Type: ApplicationFiled: July 17, 2007Publication date: April 17, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Isamu Aokura, Toshiyuki Fukuda, Yukitoshi Ota, Keiji Miki
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Publication number: 20070138638Abstract: In a semiconductor device having a multilayer interconnection structure, wires are formed by a damascene process, at least part of electrode pads includes a first conductive layer having a region provided for an electrical connection with an external unit. Herein, the first conductive layer is formed on a passivation film that is formed a semiconductor substrate and is indispensable for the multilayer interconnection structure.Type: ApplicationFiled: November 9, 2006Publication date: June 21, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Yukitoshi Ota, Noriyuki Nagai, Tsuyoshi Hamatani
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Publication number: 20070029641Abstract: A seal ring is continuously formed along a boundary between a semiconductor element region and a scribe grid region, auxiliary parts are intermittently arranged along the seal ring, and the seal ring is constituted by a metal layer.Type: ApplicationFiled: August 3, 2006Publication date: February 8, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tsuyoshi Hamatani, Yukitoshi Ota