Patents by Inventor Yukiyasu Nakao
Yukiyasu Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10886372Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery below and horizontally overlapping a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: GrantFiled: July 30, 2019Date of Patent: January 5, 2021Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Patent number: 10707341Abstract: A semiconductor device includes: a plurality of semiconductor switching elements that are a plurality of MOSFETs each including a Schottky barrier diode; a first ohmic electrode disposed above a first region of a well region and electrically connected to the first region, the first region being on the opposite side from a predefined region; a first Schottky electrode disposed on a semiconductor layer exposed at the first region of the well region; and a line electrically connected to the first ohmic electrode, the first Schottky electrode, and a source electrode. The device enables reduction of a breakdown in a gate insulating film.Type: GrantFiled: June 26, 2017Date of Patent: July 7, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Kohei Ebihara, Shiro Hino
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Publication number: 20200185517Abstract: A semiconductor device includes: a plurality of semiconductor switching elements that are a plurality of MOSFETs each including a Schottky barrier diode; a first ohmic electrode disposed above a first region of a well region and electrically connected to the first region, the first region being on the opposite side from a predefined region; a first Schottky electrode disposed on a semiconductor layer exposed at the first region of the well region; and a line electrically connected to the first ohmic electrode, the first Schottky electrode, and a source electrode. The device enables reduction of a breakdown in a gate insulating film.Type: ApplicationFiled: June 26, 2017Publication date: June 11, 2020Applicant: Mitsubishi Electric CorporationInventors: Yukiyasu NAKAO, Kohei EBIHARA, Shiro HINO
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Publication number: 20190355821Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: ApplicationFiled: July 30, 2019Publication date: November 21, 2019Applicant: Mitsubishi Electric CorporationInventors: Yukiyasu NAKAO, Masayuki IMAIZUMI, Shuhei NAKATA, Naruhisa MIURA
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Patent number: 10418444Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: GrantFiled: April 4, 2014Date of Patent: September 17, 2019Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Patent number: 9874596Abstract: The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.Type: GrantFiled: March 10, 2014Date of Patent: January 23, 2018Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Shoyu Watanabe, Akihiro Koyama, Shigehisa Yamamoto, Yukiyasu Nakao, Kazuya Konishi
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Publication number: 20160003889Abstract: The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.Type: ApplicationFiled: March 10, 2014Publication date: January 7, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shoyu WATANABE, Akihiro KOYAMA, Shigehisa YAMAMOTO, Yukiyasu NAKAO, Kazuya KONISHI
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Patent number: 9093361Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.Type: GrantFiled: March 7, 2012Date of Patent: July 28, 2015Assignee: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Akihiko Furukawa, Yukiyasu Nakao, Tomokatsu Watanabe, Masayoshi Tarutani, Yuji Ebiike, Masayuki Imaizumi, Sunao Aya
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Patent number: 9006819Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.Type: GrantFiled: February 8, 2011Date of Patent: April 14, 2015Assignee: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
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Publication number: 20140299888Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: ApplicationFiled: April 4, 2014Publication date: October 9, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu NAKAO, Masayuki IMAIZUMI, Shuhei NAKATA, Naruhisa MIURA
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Patent number: 8723259Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: GrantFiled: February 23, 2010Date of Patent: May 13, 2014Assignee: Mitsubishi Electric CorporationInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Publication number: 20140077232Abstract: A semiconductor device capable of suppressing time variation of a threshold voltage and a method of manufacturing the same. A semiconductor device according to the present invention comprises a drift layer formed on a semiconductor substrate, first well regions formed in a surface layer of the drift layer, being apart from one another, a gate insulating film formed, extending on the drift layer and each of the first well regions, a gate electrode selectively formed on the gate insulating film, a source contact hole penetrating through the gate insulating film and reaching the inside of each of the first well regions, and a residual compressive stress layer formed on at least a side surface of the source contact hole, in which a compressive stress remains.Type: ApplicationFiled: March 7, 2012Publication date: March 20, 2014Applicant: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Akihiko Furukawa, Yukiyasu Nakao, Tomokatsu Watanabe, Masayoshi Tarutani, Yuji Ebiike, Masayuki Imaizumi, Sunao Aya
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Publication number: 20130020587Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type which is formed on a first main surface of the semiconductor substrate, a second well region of a second conductivity type which is formed to surround a cell region of the drift layer, and a source pad for electrically connecting the second well regions and a source region of the cell region through a first well contact hole provided to penetrate a gate insulating film on the second well region, a second well contact hole provided to penetrate a field insulating film on the second well region and a source contact hole.Type: ApplicationFiled: February 8, 2011Publication date: January 24, 2013Applicant: Mitsubishi Electric CorporationInventors: Shiro Hino, Naruhisa Miura, Shuhei Nakata, Kenichi Ohtsuka, Shoyu Watanabe, Akihiko Furukawa, Yukiyasu Nakao, Masayuki Imaizumi
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Patent number: 8252672Abstract: A method of manufacturing a silicon carbide semiconductor device having a silicon carbide layer, the method including a step of implanting at least one of Al ions, B ions and Ga ions having an implantation concentration in a range not lower than 1E19 cm?3 and not higher than 1E21 cm?3 from a main surface of the silicon carbide layer toward the inside of the silicon carbide layer while maintaining the temperature of the silicon carbide layer at 175° C. or higher, to form a p-type impurity layer; and forming a contact electrode whose back surface establishes ohmic contact with a front surface of the p-type impurity layer on the front surface of the p-type impurity layer.Type: GrantFiled: November 7, 2008Date of Patent: August 28, 2012Assignee: Mitsubishi Electric CorporationInventors: Tomokatsu Watanabe, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
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Publication number: 20110278599Abstract: A SiC semiconductor device capable of increasing a switching speed without destroying a gate insulating film. In addition, in a SiC-MOSFET including an n-type semiconductor substrate formed of SiC, a p-type semiconductor layer is entirely or partially provided on an upper surface of a p-type well layer that has a largest area of the transverse plane among a plurality of p-type well layers provided in an n-type drift layer and is arranged on an outermost periphery immediately below a gate electrode pad. It is preferable that a concentration of an impurity contained in the p-type semiconductor layer be larger than that of the p-type well layer.Type: ApplicationFiled: February 23, 2010Publication date: November 17, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Yukiyasu Nakao, Masayuki Imaizumi, Shuhei Nakata, Naruhisa Miura
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Publication number: 20090250705Abstract: A p base ohmic contact of a silicon carbide semiconductor device consists of a p++ layer formed by high-concentration ion implantation and a metal electrode. Since the high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure, a method for implantation at high temperatures is used. In terms of switching loss and the like of devices, it is desirable that the resistivity of the p base ohmic contact should be lower. In well-known techniques, nothing is mentioned on a detailed relation among the ion implantation temperature, the ohmic contact resistivity and the process failure. Then, in the ion implantation step, the temperature of a silicon carbide wafer is maintained in a range from 175° C. to 300° C., more preferably in a range from 175° C. to 200° C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175° C. to 300° C.Type: ApplicationFiled: November 7, 2008Publication date: October 8, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Tomokatsu WATANABE, Sunao Aya, Naruhisa Miura, Keiko Sakai, Shohei Yoshida, Toshikazu Tanioka, Yukiyasu Nakao, Yoichiro Tarui, Masayuki Imaizumi
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Patent number: 6660430Abstract: There is provided a package for a non-aqueous electrolytic battery by which water invasion from outside is lowered and adhesion strength is improved over the long term, and a non-aqueous electrolytic battery having a lengthened life and high reliability. In a package for a non-aqueous electrolytic battery having a bag construction to store a battery content made by adhesion of a part of a lamination film comprising a metal layer and a resin layer, the adhesion part holds a structure capable of reacting with or absorbing an element which diffuses from the battery interior inwardly to the battery interior side.Type: GrantFiled: September 14, 2001Date of Patent: December 9, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuhiro Yoshida, Osamu Hiroi, Yukiyasu Nakao, Hisashi Shiota, Shigeru Aihara, Daigo Takemura, Hiroaki Urushibata, Michio Murai, Tetsuyuki Kurata