Patents by Inventor Yukiyoshi Nagasawa

Yukiyoshi Nagasawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7830997
    Abstract: A diversity receiving device includes a processing circuit in which receiving units, AFC and synchronizing units, and demodulating units for a plurality of systems are connected, received signal intensity detecting units 104 and 105 that detect the intensities of output signals of the respective receiving units so as to output reception intensity detection signals, a control unit that determines to select one system as a synthesis pattern of demodulation signals based on a predetermined judgment criterion according to the respective reception intensity detection signals or to select a plurality of systems so as to add demodulation signals and outputs a plurality of clock interruption control signals requesting the interruption of a clock supply to unselected systems and synthesis pattern selection signals designating a synthesis pattern of demodulation signals of the selected system, a plurality of clock supply units that interrupt the clock supply to the AFC and synchronizing units and the demodulating units
    Type: Grant
    Filed: December 1, 2006
    Date of Patent: November 9, 2010
    Assignee: Panasonic Corporation
    Inventors: Tomoharu Kawada, Akifumi Nagao, Yukiyoshi Nagasawa
  • Publication number: 20080171570
    Abstract: A wireless communications system includes: a first communications processing section for implementing a dedicated communications function that is only for the first wireless communications scheme; a second communications processing section for implementing a dedicated communications function that is only for the second wireless communications scheme; a shared transceiver section shared by the first communications processing section and the second communications processing section; a scheme selection section for selectively inputting a signal from the first communications processing section or a signal from the second communications processing section to the shared transceiver section; and a communications switching control section for indicating, to the scheme selection section, a scheme to be selected.
    Type: Application
    Filed: January 3, 2008
    Publication date: July 17, 2008
    Inventors: Akifumi Nagao, Masataka Irie, Satoshi Makimoto, Yukiyoshi Nagasawa, Takeshi Hatakeyama
  • Publication number: 20070127609
    Abstract: A diversity receiving device includes a processing circuit in which receiving units, AFC and synchronizing units, and demodulating units for a plurality of systems are connected, received signal intensity detecting units 104 and 105 that detect the intensities of output signals of the respective receiving units so as to output reception intensity detection signals, a control unit that determines to select one system as a synthesis pattern of demodulation signals based on a predetermined judgment criterion according to the respective reception intensity detection signals or to select a plurality of systems so as to add demodulation signals and outputs a plurality of clock interruption control signals requesting the interruption of a clock supply to unselected systems and synthesis pattern selection signals designating a synthesis pattern of demodulation signals of the selected system, a plurality of clock supply units that interrupt the clock supply to the AFC and synchronizing units and the demodulating units
    Type: Application
    Filed: December 1, 2006
    Publication date: June 7, 2007
    Inventors: Tomoharu Kawada, Akifumi Nagao, Yukiyoshi Nagasawa
  • Publication number: 20070098155
    Abstract: Input data is stored in input buffers provided for respective input channels. An operation channel control section controls an input data selector to allow the data stored in the input buffers to be input into an operation circuit by the block unit in a time-division manner. The operation circuit encrypts (or decrypts) the input data with an encryption key given from an encryption key selector.
    Type: Application
    Filed: July 25, 2006
    Publication date: May 3, 2007
    Inventors: Yukiyoshi Nagasawa, Tomoharu Kawada