Abstract: A pressure sensor for detecting pressure is provided. A pressure sensor including: a sensor portion that is provided in a diaphragm in a substrate; a circuit portion that is provided on the substrate and electrically connected to the sensor portion; a pad of conductivity that is provided above the substrate; and a first protective film that is provided on the pad, wherein the first protective film is also provided above the circuit portion, is provided. The first protective film may cover the circuit portion entirely. The first protective film may not cover at least part of the sensor portion. The first protective film may cover part of the sensor portion.

Abstract: A pressure sensor for detecting pressure is provided. A pressure sensor including: a sensor portion that is provided in a diaphragm in a substrate; a circuit portion that is provided on the substrate and electrically connected to the sensor portion; a pad of conductivity that is provided above the substrate; and a first protective film that is provided on the pad, wherein the first protective film is also provided above the circuit portion, is provided. The first protective film may cover the circuit portion entirely. The first protective film may not cover at least part of the sensor portion. The first protective film may cover part of the sensor portion.

Abstract: A semiconductor integrated circuit that exhibits an enhanced surge withstand voltage of a nonvolatile memory and has a reduced chip area, having a nonvolatile memory and a Zener diode connected in parallel between a write terminal and a ground terminal. The nonvolatile memory is connected to the write terminal by a write terminal line and to a common connection point by a first ground line. The cathode of the Zener diode is connected to the write terminal line. The anode of the Zener diode is connected to the specified connection point by a second ground line. The first ground line and the second ground line are connected to the specified connection point.

Abstract: A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole of a component and cannot be recognized by an image recognition apparatus. The metal film can be recognized by the image recognition apparatus. By forming a TiN film serving as a reflection prevention film on an end of the metal film, portions that can easily scatter light and a portion that cannot easily reflect light are adjacent in an alignment marker. A passivation film is formed on the interlayer insulating film and the TiN film. Recessed portions disposed in the metal film are exposed to a second opening portion formed in the passivation film and the TiN film.

Abstract: A semiconductor integrated circuit that exhibits an enhanced surge withstand voltage of a nonvolatile memory and has a reduced chip area, having a nonvolatile memory and a Zener diode connected in parallel between a write terminal and a ground terminal. The nonvolatile memory is connected to the write terminal by a write terminal line and to a common connection point by a first ground line. The cathode of the Zener diode is connected to the write terminal line. The anode of the Zener diode is connected to the specified connection point by a second ground line. The first ground line and the second ground line are connected to the specified connection point.

Abstract: A semiconductor device has a plurality of first opening portions formed in an interlayer insulating film. The surface is covered with a metal film with a surface having concavities and convexities which scatter reflected light. Size of the first opening portion is of the same level as a contact hole of a component and cannot be recognized by an image recognition apparatus. The metal film can be recognized by the image recognition apparatus. By forming a TiN film serving as a reflection prevention film on an end of the metal film, portions that can easily scatter light and a portion that cannot easily reflect light are adjacent in an alignment marker. A passivation film is formed on the interlayer insulating film and the TiN film. Recessed portions disposed in the metal film are exposed to a second opening portion formed in the passivation film and the TiN film.

Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.

Abstract: A manufacturing method of a thin film semiconductor substrate includes implanting ions at a specified depth into a semiconductor substrate, forming a bubble layer in the semiconductor substrate by vaporizing the ions through heating, bonding an insulating substrate onto the semiconductor substrate, and cleaving the semiconductor substrate along the bubble layer to form a semiconductor thin film on a side of the insulating substrate. At the forming, the semiconductor substrate is heated at a temperature in a temperature range of approximately 1000° C. to 1200° C. for a duration in a range of approximately 10 ?s to 100 ms. The heating of the semiconductor substrate is performed by using, for example, a light beam.

Abstract: Methods and apparatus for producing a semiconductor structure include: subjecting an implantation surface of a semiconductor wafer to an ion implantation process to create an exfoliation layer therein, wherein the ion implantation process includes simultaneously implanting two different species of ions into the implantation surface of the semiconductor wafer.

Abstract: A signal amplifier circuit includes a negative feedback amplifier circuit having an output terminal, a first voltage limiting device for limiting the output voltage from the negative feedback amplifier circuit, a second voltage limiting device for limiting the output voltage from the negative feedback amplifier circuit, a first reference voltage supply applying a first reference voltage to the first voltage limiting device, a second reference voltage supply applying a second reference voltage to the second voltage limiting device. The first voltage limiting device is configured to fix a lower limit saturation voltage at the first reference voltage. The second voltage limiting device is configured to fix an upper limit saturation voltage at the second reference voltage.

Abstract: A signal amplifier circuit includes a negative feedback amplifier circuit having an output terminal, a first voltage limiting device for limiting the output voltage from the negative feedback amplifier circuit, a second voltage limiting device for limiting the output voltage from the negative feedback amplifier circuit, a first reference voltage supply applying a first reference voltage to the first voltage limiting device, a second reference voltage supply applying a second reference voltage to the second voltage limiting device. The first voltage limiting device is configured to fix a lower limit saturation voltage at the first reference voltage. The second voltage limiting device is configured to fix an upper limit saturation voltage at the second reference voltage.

Abstract: A servo error signal and a defect detection signal are generated from an output signal of the pickup unit, and a servo control signal and a hold signal are generated from the servo error signal. When changing to either a servo control signal or a hold signal based on the defect detection signal generated in a defect detection signal generation circuit which has a peak hold circuit having different tracking ability, so as to perform servo control of the pickup unit, a servo error signal predetermined time before a timing to change from the servo control signal to the hold signal is used as the servo error signal used for generation of the hold signal.