Abstract: An efficient testing method is provided for internationalized software executed in a plurality of language environments. The method includes mock-translating an externalized resource file written in a first language of the internationalized software by converting characters of the first language to characters of a second language based on a conversion table; and displaying output information from the internationalized software that performs processing by referring to the mock-translated test resource file using one of a plurality of fonts prepared for respective test categories.

Abstract: Facilitating a user determination of an exclusion keyword in order to specify an efficient exclusion of an unwanted piece of data when the user narrows searching objects. Exclusion is accomplished in a system having a searching object data storage for storing pieces of searching object data, a searcher for performing a primary narrowing of the search, a common keyword extractor for extracting the common keywords associated with a piece of data, an input/output device for passing a selected keyword selected the extracted common keywords while receiving and displaying a result from an exclusion efficiency calculator. The exclusion efficiency calculator calculates exclusion efficiency and indicates a level of exclusion efficiency of data that is not associated with a selected keyword for an individual common keyword.

Abstract: A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.

Abstract: A semiconductor device design method useful for the design of microprocessor, ASIC, and high-speed high-performance LSI is intended to enhance the accuracy of delay calculation and crosstalk noise calculation, and enhance the accuracy of assessment of delay variation caused by crosstalk and checking of malfunctioning caused by crosstalk.

Abstract: According to the present invention, there is provided an automotive sunshade panel formed from a metallic hollow panel and having flanged edges and a two-dimensional curved surface or a three-dimensional curved surface formed at least partially of its central portion excepting the peripheries of the metallic hollow panel. For use in the present invention, a fabric may be laminated to at least one side of the metallic hollow panel. The metallic hollow panel is formed into a one-side expanded Roll-Bond® panel, a both-side expanded Roll-Bond® panel, a both-side flat three-layer Roll-Bond® panel or a honeycomb panel.

Abstract: The present invention is to provide a method of computing wiring capacitance to be able to get parasitic capacity depending on the wiring at high speed and with great accuracy, and to provide a method of computing signal propagation delay due to cross talk to be able to remove surplus margins at high speed when delay is predicted. In design of LSIs such as microprocessors or the like, total capacity Ctotal per unit length is determined about each of a plurality of models altering adjacent wiring ((a) no adjacent wiring, (b) one-side adjacent wiring, and (c) both-sides adjacent wiring) and/or crossing ratios ((i) 0%, (ii) 33%, (iii) 67%, and (iv) 100%) and, thereby, a library is formed from these to design the LSI. Regarding characteristic of this total capacity per unit length, the capacity depending on increase of the crossing ratio has a high increase rate in an area of a low crossing ratio, while the capacity depending on increase of the crossing ratio has the low increase rate in high crossing ratio.

Abstract: According to the present invention, there is provided an automotive sunshade panel formed from a metallic hollow panel and having flanged edges and a two-dimensional curved surface or a three-dimensional curved surface formed at least partially of its central portion excepting the peripheries of the metallic hollow panel. For use in the present invention, a fabric may be laminated to at least one side of the metallic hollow panel. The metallic hollow panel is formed into a one-side inflated Roll-Bond panel, a both-side inflated Roll-Bond panel, a both-side flat three-layer Roll-Bond panel or a honeycomb panel. In order to obtain such an automotive sunshade panel of the present invention, the metallic hollow panel is first bent in the roll circumferential direction (Y—Y axis) by means of twin rolls consisting of a rigid roll and an elastic roll, and then is subjected to a flanging process in which its longitudinal edges are flanged by press forming or roll forming.

Abstract: A memory portion and a logic circuit portion of a semiconductor device are formed on a single semiconductor substrate in which a first logic circuit block and a second logic circuit block are formed in different areas and the second logic circuit is located between a pair of memory blocks. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block. A clock signal entered at the center portion of the semiconductor chip is supplied to a plurality of first state clock distributing circuits equidistantly disposed from the center portion and then to a plurality of second stage clock distributing circuits at least equidistantly disposed from each of the first state clock distributing circuits.

Abstract: A semiconductor integrated circuit device having a memory portion and a logic circuit portion formed with a same semiconductor substrate comprising a first logic circuit block, a second logic circuit block disposed in an area different from an area in which the first logic circuit block is disposed, and a pair of memory blocks oppositely disposed so that the second logic circuit block comes in between. Data stored in the pair of memory blocks are transmitted to the second logic circuit block for processing via a memory peripheral circuit provided on the second logic circuit block. A result of the data processing is transmitted to the first logic circuit block or an external device via an input/output circuit provided in the second logic circuit block.

Abstract: A semiconductor IC device has an input/output circuit and an internal logic circuit connected with the input/output circuit formed in a main surface of a semiconductor substrate of a generally rectangular shape. The input/output circuit is divided into at least two input/output circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in a direction substantially parallel with a pair of opposite sides of the substrate. The internal logic circuit is divided into at least three logic circuit blocks in such a manner that edges of the logic circuit blocks defined by the division on the main surface of the substrate extend in the above-mentioned direction. Each of the input/output circuit blocks is sandwiched by and electrically connected with adjacently arranged two of the logic circuit blocks.

Abstract: Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.

Abstract: A semiconductor integrated circuit device has a plurality of emitter-coupled logic (ECL) gates. Separate power source wiring lines are provided for current switch circuits and emitter follower output circuits for the gates. The separate sets of power source wiring lines are respectively coupled to the corresponding external terminals of the semiconductor integrated circuit device. The power source wiring lines for each set are arranged adjacent one another on a semiconductor chip in order that they may be short circuited or kept separated depending upon the package structure of the semiconductor integrated circuit device.