Abstract: A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.

Abstract: In an apparatus for supporting test pattern generation, when an acquiring unit acquires connection information of a target circuit to be tested and an untested path, a detecting unit detects paths between all flip-flop cells in the target circuit to create an untested path list. A path extracting unit extracts tested paths and creates a tested path list. A search unit creates a search-result list. A cell extracting unit extracts an untested cell and changes end flags of the untested paths including the untested cell extracted from “0” to “1”. When all end flags in the untested path list are changed to “1”, a correcting unit corrects the connection information, so that a dummy buffer is inserted and connected to a data pin of the untested cell.

Abstract: A design support apparatus includes a unit that inputs a user net list created by using hard macro cells excluding test circuits, and a unit that arranges hard macro cells using a frame into which hard macro cells, where timing-converged physical information includes test terminals, and test circuits are embedded as arrangement/wiring information. Moreover, includes a unit that arranges and wires the test circuits using the arrangement/wiring information of the test circuit embedded into the frame, a unit that recognizes arrangement/wiring information where the arrangement/wiring information of the test circuits is removed from arrangement/wiring information obtained by wiring, and a unit outputs a net list of a logic structure.