Patents by Inventor Yuko Namiki
Yuko Namiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240158574Abstract: A polyetheretherkenote comprising a repeating unit represented by the following formula (1) and a terminal structure represented by the following formula (2):Type: ApplicationFiled: April 27, 2022Publication date: May 16, 2024Applicant: IDEMITSU KOSAN CO.,LTD.Inventors: Soshi NAMIKI, Takehiro FUJITA, Hiromu KUMAGAI, Yuko HOSHI
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Patent number: 8547744Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first word line, and a control circuit configured to control a voltage of a word line to write data to a memory cell so that data are written in order from the first word line to the second word line. In a write sequence of the first word line, the control circuit applies a writing voltage to the second word line before writing a memory cell connected to the first word line.Type: GrantFiled: July 19, 2011Date of Patent: October 1, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yuko Namiki, Mitsuaki Honma
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Patent number: 8493788Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a first even-numbered bit line, to execute a second data program in a first odd-numbered bit line, to execute a verify read of the programmed bit lines, to determine whether a value of the verify read is programmed up to a predetermined threshold value, and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line.Type: GrantFiled: March 2, 2011Date of Patent: July 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yuko Namiki, Mitsuaki Honma
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Patent number: 8374032Abstract: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.Type: GrantFiled: June 15, 2011Date of Patent: February 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yuko Namiki, Takuya Futatsuyama, Yuui Shimizu
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Patent number: 8194465Abstract: A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.Type: GrantFiled: September 16, 2010Date of Patent: June 5, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yuko Namiki, Takuya Futatsuyama
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Publication number: 20120020154Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first word line, and a control circuit configured to control a voltage of a word line to write data to a memory cell so that data are written in order from the first word line to the second word line. In a write sequence of the first word line, the control circuit applies a writing voltage to the second word line before writing a memory cell connected to the first word line.Type: ApplicationFiled: July 19, 2011Publication date: January 26, 2012Inventors: Yuko NAMIKI, Mitsuaki Honma
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Publication number: 20110242892Abstract: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.Type: ApplicationFiled: June 15, 2011Publication date: October 6, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yuko NAMIKI, Takuya Futatsuyama, Yuui Shimizu
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Publication number: 20110216599Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a first even-numbered bit line, to execute a second data program in a first odd-numbered bit line, to execute a verify read of the programmed bit lines, to determine whether a value of the verify read is programmed up to a predetermined threshold value, and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line.Type: ApplicationFiled: March 2, 2011Publication date: September 8, 2011Inventors: Yuko NAMIKI, Mitsuaki HONMA
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Patent number: 7965555Abstract: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.Type: GrantFiled: February 2, 2009Date of Patent: June 21, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yuko Namiki, Takuya Futatsuyama, Yuui Shimizu
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Publication number: 20110069557Abstract: A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.Type: ApplicationFiled: September 16, 2010Publication date: March 24, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Yuko NAMIKI, Takuya Futatsuyama
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Publication number: 20090238003Abstract: A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.Type: ApplicationFiled: February 2, 2009Publication date: September 24, 2009Applicant: Kabushiki Kaisha ToshibaInventors: Yuko NAMIKI, Takuya Futatsuyama, Yuui Shimizu