Abstract: A memory system includes a non-volatile memory including a plurality of memory cells; and a controller. The controller is configured to perform a multi-step write operation to write multi-bit data with respect to each of target memory cells through a first programming to set a first threshold voltage and then a second programming to set a second threshold voltage. The controller, during the multi-step write operation, determines a time period elapsed from a first time at which the first programming with respect to a first memory cell of the target memory cells has been performed, and varies a second time at which the second programming with respect to the first memory cell is performed based on whether the time period is greater than a first threshold.

Abstract: A memory system includes a non-volatile memory in which data is stored in a plurality of pages including a first page and a second page and a memory controller. The controller is configured to perform a first write operation on the first page at a first time, perform a second write operation on the second page at a second time after the first time, perform a first read operation on the first page at a time after the first time using a first parameter and store a first index value in association with the first page and the first parameter, and determine a second parameter for a second read operation to be performed on the second page using a time difference between the first time and the second time and the first index value stored in association with the first page.

Abstract: A memory controller receives first, second, and third data by first, second, and third reads, specifying a first address, and respectively specifying first, second, and third read voltages higher in this order. The controller instructs a memory to execute a fourth read specifying a fourth read voltage lower than the first read voltage and the first address when a first difference between a first-value-bit count of the first data and an expected value is smaller than a second difference between a first-value-bit count of the third data and the expected value. The memory controller instructs the memory to execute a fifth read specifying a fifth read voltage higher than the third read voltage and the first address when the first difference is larger than the second difference.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of memory chips and a controller. The controller acquires a first command from a first queue, transmits the acquired first command to a first memory chip, thereafter acquires a second command from a second queue, and transmit the acquired second command to a second memory chip when a first command processing speed based on a time until execution of a command using the first memory chip is completed after transmission of the command to the first memory chip is started is lower than a second command processing speed based on a time until execution of a command using the second memory chip is completed after transmission of the command to the second memory chip is started.

Abstract: A memory system includes a non-volatile memory in which data is stored in a plurality of pages including a first page and a second page and a memory controller. The controller is configured to perform a first write operation on the first page at a first time, perform a second write operation on the second page at a second time after the first time, perform a first read operation on the first page at a time after the first time using a first parameter and store a first index value in association with the first page and the first parameter, and determine a second parameter for a second read operation to be performed on the second page using a time difference between the first time and the second time and the first index value stored in association with the first page.

Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

Abstract: A memory system includes a memory chip and a memory controller. The memory chip has a first plane and a second plane. A threshold voltage corresponding to multiple bit data is set for each of the memory cells. The memory controller causes the memory chip to execute a first read process on the first plane and the second plane in parallel by using a plurality of first read voltages different from each other for the first plane and the second plane. The first read process being a process of reading a data group of one bit among the multiple bits by using the first read voltages. The memory controller subsequently adjusts the voltage levels of the first read voltages on the basis of the data group read from the memory cells of the first plane and the data group read from the memory cells of the second plane.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of memory chips and a controller. The controller acquires a first command from a first queue, transmits the acquired first command to a first memory chip, thereafter acquires a second command from a second queue, and transmit the acquired second command to a second memory chip when a first command processing speed based on a time until execution of a command using the first memory chip is completed after transmission of the command to the first memory chip is started is lower than a second command processing speed based on a time until execution of a command using the second memory chip is completed after transmission of the command to the second memory chip is started.