Patents by Inventor Yuko Yokota

Yuko Yokota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160341759
    Abstract: A sensor comprising: a mass element; a frame surrounding the mass element; a connecting body having flexibility, and connecting the mass element to the frame; a pressure detecting unit; and an acceleration detecting unit. The mass element comprises: a main portion comprising a through-hole passing therethrough from the top surface to the bottom surface; a mounting portion connected to the top surface of the main portion, and surrounding an outer periphery of the through-hole; a first cover portion having flexibility, connected to the mounting portion and covering the through-hole; and a second cover portion, disposed on the bottom surface of the main portion, covering the through-hole, and deformable less than the first cover portion when received an external force.
    Type: Application
    Filed: January 26, 2015
    Publication date: November 24, 2016
    Inventors: Tokuichi YAMAJI, Yuko YOKOTA, Atsuo HATATE, Hiroki ISHIKAWA, Takeshi SUZUKI, Hideaki ASAO
  • Patent number: 9236135
    Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: January 12, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshihiko Kamata, Yuko Yokota
  • Patent number: 9171631
    Abstract: According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 27, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshihiko Kamata, Yuko Yokota, Koji Tabata, Tomoyuki Hamano, Mario Sako
  • Publication number: 20150262691
    Abstract: According to one embodiment, a nonvolatile semiconductor storage device includes a memory cell, a voltage generator configured to output a first voltage and a second voltage, and a controller. The controller executes a write operation, which includes a first read operation, a program operation, and a verify operation. The controller executes the first read operation before the program operation and the verify operation. The controller executes the first read operation by applying the first voltage to a gate of the memory cell. The controller executes an erase verify operation by applying the second voltage to the gate of the memory cell. The first voltage is higher than the second voltage.
    Type: Application
    Filed: September 11, 2014
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshihiko KAMATA, Yuko YOKOTA
  • Publication number: 20130279255
    Abstract: According to one embodiment, a semiconductor memory device includes a first transistor, a detector, and a second transistor. The first transistor is capable of transferring a first voltage to a bit line. The detector reads data held by a memory cell connected to the bit line. The second transistor is capable of transferring a second voltage and a third voltage to the detector. The second voltage is generated by a source different from a source of the first voltage. The third voltage is larger than the second voltage. The second transistor charges the detector to one of the second voltage and the third voltage, while the first transistor transferring the first voltage to the bit line.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 24, 2013
    Inventors: Yoshihiko KAMATA, Yuko YOKOTA, Koji TABATA, Tomoyuki HAMANO, Mario SAKO
  • Publication number: 20130279254
    Abstract: According to one embodiment, a semiconductor memory storage apparatus includes an array, a sense amplifier, and a controller. The array includes a memory cell. The sense amplifier includes a first latch and a second latch. The first latch and the second latch are capable of storing a data read out from the memory cell. The controller performs a first operation, a second operation, and a third operation. In the first operation, the controller transfers an inverted data in the first latch to the first node and transfers the data in the second latch. In the second operation, the controller transfers the data in the first latch to the first node and transfers an inverted data in the second latch.
    Type: Application
    Filed: March 15, 2013
    Publication date: October 24, 2013
    Inventors: Yoshihiko KAMATA, Koji TABATA, Mitsuhiro KOGA, Tomoyuki HAMANO, Yuko YOKOTA
  • Patent number: 5774713
    Abstract: A file creation method for constructing a system environment, a system environment constructing method, and a command start system. Prior to using the system, a plurality of application programs are classified into field groups, which are further divided into groups on the basis of functions thereof. The groups are further divided into input items on the basis of command options. Every layer of a hierarchy is ranked. Character strings are assigned to icons, button and data input frame so as to represent names or functions of groups. Files are created for every layer and group so that they contain information on the ranks, icons, and linkages between files. The files are read out and displayed in a top-down manner according to their ranks, so that a specific application program can be designated by selecting at least one icon or option, or entering an input item. Thereafter, the application program will be started.
    Type: Grant
    Filed: September 26, 1994
    Date of Patent: June 30, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yuko Yokota
  • Patent number: 5163015
    Abstract: Characteristics of a coupled system, which consists of a plurality of unit structures coupled together, are analyzed accurately and quickly by providing, between calculating means for calculating transfer function matrices concerning unit structures and coupling means for coupling together transfer function matrices according to the definitions of coupling, co-ordinate conversion means for converting transfer function matrices into those in the overall system.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: November 10, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yuko Yokota