Patents by Inventor Yuko Yoshifuku

Yuko Yoshifuku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9035392
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Grant
    Filed: February 20, 2014
    Date of Patent: May 19, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
  • Publication number: 20140239406
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Nobuhiro TSUDA, Hidekatsu NISHIMAKI, Hiroshi OMURA, Yuko YOSHIFUKU
  • Patent number: 8710552
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
  • Publication number: 20120261723
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Nobuhiro TSUDA, Hidekatsu NISHlMAKI, Hiroshi OMURA, Yuko YOSHIFUKU
  • Patent number: 8237203
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Nobuhiro Tsuda, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku
  • Publication number: 20100044755
    Abstract: A pMIS region is provided between a boundary extending in a first direction and passing through each of a plurality of standard cells and a first peripheral edge. An nMIS region is provided between the boundary and a second peripheral edge. A power supply wiring and a grounding wiring extend along the first and second peripheral edges, respectively. A plurality of pMIS wirings and a plurality of nMIS wirings are arranged on a plurality of first virtual lines and a plurality of second virtual lines, respectively, extending in the first direction and arranged with a single pitch in a second direction. The first virtual line that is the closest to the boundary and the second virtual line that is the closest to the boundary have therebetween a spacing larger than the single pitch.
    Type: Application
    Filed: August 5, 2009
    Publication date: February 25, 2010
    Inventors: Nobuhiro TSUDA, Hidekatsu Nishimaki, Hiroshi Omura, Yuko Yoshifuku