Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Abstract: In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.

Abstract: A multi-core processor includes a plurality of former-stage cores that perform parallel processing using a plurality of pipelines covering a plurality of stages. In the pipelines, the former-stage cores perform stages ending with an instruction decode stage; stages starting with an instruction execution stage are executed by a latter-stage core. A dynamic load distribution block refers to decode results in the instruction decode stage and controls to assign the latter-stage core with a latter-stage-needed decode result being a decode result whose processing needs to be executed in the latter-stage core.

Abstract: In one embodiment of the present invention, processor 1000 comprising a plurality of processor cores for processing an instruction-execution sequence is provided. Signal path 140 that is able to communicate an inter-core interrupt signal fint is connected to at least two processor cores 100A and 100B. Each core of the at least two cores has an inter-core interrupt count setting register (ICSR) 110 and a FIFO counter 120. Inter-core interrupt synchronization function, inter-core interrupt generation function, and FIFO counter updating function are implemented to the every core. In embodiments of the present invention, a core and a method therefor are also provided.

Abstract: A simulation device capable of verifying coordinated operation of software and hardware faster and more accurately. The simulation device has a framework including a virtual OS and a virtual CPU to execute software under test. The virtual OS and CPU also serve as a first scheduler that manages an execution schedule for the software under test. The framework includes a communication interface for communication between the software under test and hardware models. A second scheduler manages simulation processes of the framework and the hardware model. The virtual OS and CPU release their execution right to the second scheduler according to the execution schedule of the software under test.

Abstract: Modem comprising a delta modulation (DM) encoder and a DM decoder which has noise-reducing capability in the demodulation of encoded binary pulse signals representative of constant amplitude signals. The DM decoder includes a 1-click delay circuit operable in conjunction with a logic circuit and an integrator to produce a demodulated output signal which is the same as the preceding signal when the input signals to the DM encoder are constant amplitude signals, thereby eliminating are substantially reducing granular noise arising from a constant analog input to the modem without requiring a special filter. The logic circuit of the DM decoder may be an exclusive NOR gate which compares the 1-clock delayed binary pulse signal with the binary pulse signal and provides a control signal output based upon the comparison. The control signal output from the exclusive NOR gate controls the output of the integrator and enables the integrator to produce a substantially noise-free demodulated output signal.