Abstract: An overhead traveling vehicle configured to transport wafers includes a mobile drive unit configured to move along a predetermined route on one side of a ceiling and a hoist unit configured to move along the predetermined route according to a position of the mobile drive unit. The mobile drive unit and the hoist unit respectively include a first magnet and a second magnet so that the hoist unit may be hung on the ceiling by the magnetic force generated between the magnets.

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A semiconductor electronic device structure includes an active area array disposed in a substrate, an isolation structure, a plurality of recessed gate structures, a plurality of word lines, and a plurality of bit lines. The active area array a plurality of active area columns and a plurality of active area rows, defining an array of active areas. The substrate has two recesses formed at the central region thereof. Each recessed gate structure is respectively disposed in the recess. A protruding structure is formed on the substrate in each recess. A STI structure of the isolation structure is arranged between each pair of adjacent active area rows. Word lines are disposed in the substrate, each electrically connecting the gate structures there-under. Bit lines are disposed above the active areas, forming a crossing pattern with the word lines.

Abstract: A planer head is provided with an axis; a plurality of elongated knife carrier assemblies circumferentially formed on the axis, each of the knife carrier assemblies including a first surface, a second surface butted on both the first surface thereof and the first surface of an adjacent one of the knife carrier assemblies, and a plurality of threaded holes disposed on the first surface; a plurality of knives each having a plurality of through holes; and a plurality of threaded fasteners driven the through holes into the threaded holes to secure the knives to the first surfaces of the knife carrier assemblies. Along the axis, the knives are equally spaced apart.

Abstract: A planer head is provided with a cylindrical body; an axis formed through the body; a knife carrier assembly formed with the cylindrical body and including a first knife carrier and second knife carriers circumferentially equally spaced apart, each of the first and second knife carriers including a flat front surface, a flat rear surface, and a curved, intermediate surface; and threaded holes formed on the front surface of each of the first and second knife carries; an elongated first knife including first through holes; second knives each including second through holes; first fasteners driven through the first through holes into the threaded holes to secure the first knife to the front surface of the first knife carrier; and second fasteners driven through the second through holes into the threaded holes to secure the second knives to the front surface of each second knife carrier.

Abstract: A wafer cassette transportation method includes the steps: (a) Provide a monitoring system, overhead platforms, a detection system, and a plurality of transportation systems; (b) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits first signals to the monitoring system; (c) The monitoring system reads the first signals and instructs one of the transportation systems to move the wafer cassette to an empty overhead platform; (d) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits second signals to the monitoring system; and (e) The monitoring system reads the second signals and instructs another transportation system to move the wafer cassette away from the overhead platform, so as to enhance the transportation speed of the wafer cassette and lower the manufacturing cost. The present invention further provides a wafer cassette transportation system.

Abstract: An automatic recovery and transport system includes a manufacture execution system, a path planning system electrically connected with the manufacture execution system, a vehicle control system electrically connected with the path planning system, a plurality of vehicles electrically connected with the vehicle control system; and an alarm system electrically connected with the path planning system and the vehicle control system. The alarm system will command the path planning system to command the vehicle control system to drive the vehicle about to stop to enter the maintenance area immediately. Accordingly, the stability and the work efficiency of the whole system are improved. The present invention also provides a method for executing an automatic recovery and transport system.

Abstract: An automatic recovery and transport system includes a manufacture execution system, a path planning system electrically connected with the manufacture execution system, a vehicle control system electrically connected with the path planning system, a plurality of vehicles electrically connected with the vehicle control system; and an alarm system electrically connected with the path planning system and the vehicle control system. The alarm system will command the path planning system to command the vehicle control system to drive the vehicle about to stop to enter the maintenance area immediately. Accordingly, the stability and the work efficiency of the whole system are improved. The present invention also provides a method for executing an automatic recovery and transport system.

Abstract: An automatic transport system includes: an overhead rail module having a plurality of transport rail sets, the transport rail sets each defining a bay; a plurality of overhead hoist transport vehicles movably disposed in the overhead rail module; and a control module electrically connected to the overhead hoist transport vehicles, the control module being used to control the number of the overhead hoist transport vehicles in the bays. Via this arrangement, the control module keeps some overhead hoist transport vehicles staying in each bay, thereby preventing one of the bays from having no overhead hoist transport vehicle to immediately use. This invention further provides a control method of the automatic transport system.

Abstract: A cross-fab control system and a method for using the said system are disclosed. The said system comprises a first transport system, a second transport system, a cross-area control system, and a stocker. The first transport system connects the cross-area control system. The stocker connects the second transport system and the cross-area control system. The cross-area control system is utilized to identify Front Opening Unified Pod (FOUP) data on the stocker. By the assistance of the cross-area control system, the first transport system will transport the FOUP to destination through optimize path and avoid FOUP staying on the stocker with no transport command.

Abstract: A wafer cassette transportation method includes the steps: (a) Provide a monitoring system, overhead platforms, a detection system, and a plurality of transportation systems; (b) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits first signals to the monitoring system; (c) The monitoring system reads the first signals and instructs one of the transportation systems to move the wafer cassette to an empty overhead platform; (d) The detection system detects whether or not any overhead platform has a wafer cassette and generates and transmits second signals to the monitoring system; and (e) The monitoring system reads the second signals and instructs another transportation system to move the wafer cassette away from the overhead platform, so as to enhance the transportation speed of the wafer cassette and lower the manufacturing cost. The present invention further provides a wafer cassette transportation system.

Abstract: A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base structure is then treated with an anisotropic annealing source inclined in the source-to-drain direction of the base structure relative to the normal of the substrate, such that one of the source and drain extensions is shadowed by the gate and the other is annealed more.

Abstract: A method for fabricating an asymmetric semiconductor device is provided. A substrate formed with at least one base structure of MOSFET thereon is provided, wherein the base structure includes a gate over the substrate and a source extension and a drain extension in the substrate beside the gate. The base structure is then treated with an anisotropic annealing source inclined in the source-to-drain direction of the base structure relative to the normal of the substrate, such that one of the source and drain extensions is shadowed by the gate and the other is annealed more.

Abstract: A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.

Abstract: A method of forming a transistor involves firstly forming at least one gate structure on a semiconductor substrate. Then, a surface cleaning process is performed. In the surface cleaning process, a chemical oxidation method is utilized for forming a first oxide layer on a surface of the semiconductor substrate not covered with the gate structure and the first oxide layer is removed subsequently. Finally, a selective epitaxial growth method is utilized for forming a first epitaxial layer on the surface of the semiconductor substrate.

Abstract: A method for preventing to form a spacer undercut in SEG preclean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a native oxide layer upon a surface of a semiconductor substrate is removed. Hence, the clean surface on the semiconductor substrate is obtained. This method includes the steps as follows: Firstly, the native oxide layer upon the surface of the semiconductor substrate is removed by DHF (HF in deionized water) solution. Then, etching the first spacer and the second spacer at the same time by HFEG (HF diluted by ethylene glycol) solution. Also, the native oxide upon the semiconductor substrate is removed. Therefore, it obtains the clean semiconductor surface without a serious spacer undercut.

Abstract: A method of forming a transistor involves firstly forming at least one gate structure on a semiconductor substrate. Then, a surface cleaning process is performed. In the surface cleaning process, a chemical oxidation method is utilized for forming a first oxide layer on a surface of the semiconductor substrate not covered with the gate structure and the first oxide layer is removed subsequently. Finally, a selective epitaxial growth method is utilized for forming a first epitaxial layer on the surface of the semiconductor substrate.

Abstract: A method for forming a junction region of a semiconductor device is disclosed. The steps of the method include providing a semiconductor substrate. A gate structure is formed on the semiconductor substrate. A dopant is implanted into the semiconductor substrate to form the junction region. An insulator layer is formed on the gate structure and the semiconductor substrate. A carbon-containing plasma treatment is performed to the insulator layer. A spacer is formed on a side-wall of the gate structure and the dopant is implanted into the semiconductor substrate to form a source/drain region next to the junction region. A heat treatment is performed to the semiconductor substrate.

Abstract: A method of manufacturing a MOS transistor is provided. A gate insulation layer and a conductive layer are sequentially formed over a substrate. A pre-amorphization implantation is carried out to amorphize the conductive layer. The conductive layer and the gate insulation layer are patterned to form a gate structure. A first spacer is formed on the sidewall of the gate structure. A second pre-amorphization implantation is carried out to amorphize a portion of the substrate. A doped source/drain extension region is formed in the substrate on each side of the first spacer. A second spacer is formed on the sidewall of the first spacer and then a doped source/drain region is formed in the substrate on each side of the second spacer. A solid phase epitaxial process is carried out to convert the doped source/drain extension region and the doped source/drain region into a source/drain terminal. In the pre-amorphization implantations, dopants having an ionic radius greater than the germanium ion are used.

Abstract: A method for preventing to form a spacer undercut in SEG pre-clean process is provided. This present invention utilizes HFEG solution to etch the first spacer and the second spacer simultaneously, which can prevent from producing a spacer undercut, meanwhile; a native oxide layer upon a surface of a semiconductor substrate is removed. Hence, the clean surface on the semiconductor substrate is obtained. This method includes the steps as follows: Firstly, the native oxide layer upon the surface of the semiconductor substrate is removed by DHF (HF in deionized water) solution. Then, etching the first spacer and the second spacer at the same time by HFEG (HF diluted by ethylene glycol) solution. Also, the native oxide upon the semiconductor substrate is removed. Therefore, it obtains the clean semiconductor surface without a serious spacer undercut.