Abstract: A multispectral imaging system for generating imagery from a broad range of electromagnetic radiation. In a preferred embodiment, the system comprises an image processor unit having a plurality of dedicated inputs formed thereon, each of which connectable to a respective one of a plurality of sensors wherein each sensor is designed to detect wavelengths emanating from a specific spectral region. The image processor unit receives data from a respective sensor, processes such data, and generates an output that is fed to a multimedia controller and computer, the latter being designed to either digitally store, display or provide a printout of the imaging data. In a preferred embodiment, the multimedia controller computer is further designed to transfer such imagery data to a variety of data links to users interfacing with the imaging system. The system may further be modified to accommodate endoscopic sensors for use in procedures related thereto.

Abstract: An analog neural network element includes one or more EEPROMs as analog, reprogrammable synapses applying weighted inputs to positive and negative term outputs which are combined in a comparator. In one embodiment a pair of EEPROMs is used in each synaptic connection to separately drive the positive and negative term outputs. In another embodiment, a single EEPROM is used as a programmable current source to control the operation of a differential amplifier driving the positive and negative term outputs. In a still further embodiment, an MNOS memory transistor replaces the EEPROM or EEPROMs. These memory elements have limited retention or endurance which is used to simulate forgetfulness to emulate human brain function. Multiple elements are combinable on a single chip to form neural net building blocks which are then combinable to form massively parallel neural nets.

Abstract: A multichip electronic package uses a silicon substrate for chip mounting and interconnects, micro-machined inverted and non-inverted truncated vias for intrinsically hermetically sealed I/O connections, and an anodically bonded silicon cover, with support posts. Stacked, colocated and inverted vias are provided for increased chip and interconnect density within an intrinsically sealed, thermally matched package.

Abstract: This combination process enables both MNOS and CMOS devices to be fabricated upon the same wafer in very large scale integration systems. Conventional moat isolation techniques are replaced with low temperature ion implantation processing to accomplish substrate isolation. Both n and p channel MOS transistor diffusions and field oxidations are processed concurrently. Also, this process utilizes bulk silicon wafer material rather than epitaxial wafer material as the substrate.

Abstract: The disclosed solid state mass memory system comprises an adaptive, wafer scale integration, nonvolatile mass memory system organized as a stack of individual memory wafer modules with a memory system control means.

Abstract: An MNOS nonvolatile memory array employing single-element-per-bit storage and two-element-per-bit sensing utilizing a threshold referenced sense amplifier is organized such that the two legs of the sensing circuit are in substantial electrical balance during sensing.

Abstract: A method for fabricating MOS and MNOS transistors on a common substrate which strips the silicon nitride required for MNOS operation away from areas where it is not required. The removal of the nitride from the MOS gate eliminates cumulative threshold instability and allows separate optimization of both MOS and MNOS structures in a single process. Removal of nitride from other areas such as the contact regions prevents undercut structures of nitride dielectric from being formed during contact hole fabrication and thus minimizes reliability problems and yield limitations. Further an improved MNOS structure is produced which has strips of nitride in the gate region spaced apart from the diffused regions, thereby minimizing diode breakdown and long term threshold instability.

Abstract: The disclosed device uses an interconnect switch for the selective coupling of serial memory elements in series with other memory elements. A control unit may test elements, designate some of the elements as operable for use and designate other elements as spares. The memory system is defined by the states of interconnection which couple the memory elements either for operation or for sparing, and which uncouple the defective memory element from use in the system. Upon the failure of an element which is being used the control unit can switch out the defective memory cell and switch in a replacement element or simply bypass the defective element. This technique is particularly useful for wafer scale integration where a plurality of functional elements are contained on a single wafer; particularly in memory arrays which are individually addressable. However, this technique also allows the selective replacing of elements within the particular array to ensure the proper number of memory cells within the array.

Abstract: A method for fabricating MOS and MNOS transistors on a common substrate which strips the silicon nitride required for MNOS operation away from areas where it is not required. The removal of the nitride from the MOS gate eliminates cumulative threshold instability and allows separate optimization of both MOS and MNOS structures in a single process. Removal of nitride from other areas such as the contact regions prevents undercut structures of nitride dielectric from being formed during contact hole fabrication and thus minimizes reliability problems and yield limitations. Further an improved MNOS structure is produced which has strips of nitride in the gate region spaced apart from the diffused regions, thereby minimizing diode breakdown and long term threshold instability.

Abstract: The disclosed apparatus uses an associative memory technique for the selective coupling of circuit elements to a data bus wherein each element is assigned an associative address and is coupled to the data bus when it receives said address on its address lines. The apparatus further comprises a reconfiguration control unit for assigning associative addresses to all elements, allowing said elements to be addressed at random. When one function element is to be substituted for another, the reconfiguration control unit assigns the address of the replaced element to the replacing element. In this way, the user continues to use the same address, making an element replacement transparent to the user, thereby avoiding reprogramming by the user. In the preferred embodiment the associative address is stored in nonvolatile memory so that it will not be lost when power is turned off, but is electrically reprogrammable if necessary or desired.

Abstract: A method for fabricating a variable threshold IGFET free of parasitic effects and the "floating gate" effect.The method comprises forming a semi-conductive substrate of a first conductivity type material, forming a pair of laterally spaced diffusion regions of opposite conductivity type to the substrate material adjacent one surface of the substrate and forming a variable thickness oxide layer having a portion of minimum thickness with a predetermined width at least partially overlying the interstitial portion of the substrate, a portion of intermediate thickness substantially greater than the minimum thickness and partially overlying the interstitial substrate portion and at least one of the pair of spaced diffusion regions, and a remaining portion of maximum thickness substantially greater than the intermediate thickness.

Abstract: A method for fabricating a variable threshold IGFET free of parasitic effects and the "floating gate" effect. The IGFET includes an oxide layer having a portion of minimum thickness in the region thereof overlying an interstitial portion of a semiconductive substrate having a pair of spaced semiconductive diffusion regions, a portion of intermediate thickness partially overlying at least one of the pair of diffusion regions and the interstitial substrate portion, and a remaining portion of maximum thickness. The oxide layer portion of minimum thickness has a width greater than the width of an overlying electrically conductive gate electrode; the oxide layer portion of intermediate thickness has a width less than the width of the overlying electrode.