Abstract: The present application discloses a verification system and method for an operation result based on a reconfigurable butterfly unit. The system is applicable to a digital signal processing (DSP) chip. The DSP chip includes a reconfigurable butterfly unit. The reconfigurable butterfly unit may be reconfigured into two modes: a first verification mode and a second verification mode. The system includes: a controller, a memory, a verification unit, a first data gating unit, and a second data gating unit. The technical solution in the present application is used to overcome the disadvantage that an existing verification system and an existing verification method consume large hardware resources, thereby reducing the implementation costs of operation result verification.

Abstract: The application discloses a data processing device, a data processing method and a digital signal processing device. The data processing device is used to reduce computing amount by reading and writing operation of memory. The data processing device comprises: a module for calculating reduced coefficient matrices, a storage module, a module for modifying reduced coefficient matrices, a module for triangular inversing, a module for obtaining inversion matrices and a module for correcting reverse result.

Abstract: The present application discloses a verification system and method for an operation result based on a reconfigurable butterfly unit. The system is applicable to a digital signal processing (DSP) chip. The DSP chip includes a reconfigurable butterfly unit. The reconfigurable butterfly unit may be reconfigured into two modes: a first verification mode and a second verification mode. The system includes: a controller, a memory, a verification unit, a first data gating unit, and a second data gating unit. The technical solution in the present application is used to overcome the disadvantage that an existing verification system and an existing verification method consume large hardware resources, thereby reducing the implementation costs of operation result verification.

Abstract: The application discloses a data processing device, a data processing method and a digital signal processing device. The data processing device is used to reduce computing amount by reading and writing operation of memory. The data processing device comprises: a module for calculating reduced coefficient matrices, a storage module, a module for modifying reduced coefficient matrices, a module for triangular inversing, a module for obtaining inversion matrices and a module for correcting reverse result.

Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.

Abstract: The present invention provides a program counter compression method and a hardware circuit thereof. The compression method of the present invention includes the following steps: step (1), acquiring execution condition of instructions sent by a processor and classifying and screening said instructions based on said execution condition of the instructions; step (2), executing differential operation on instruction count values of the objective classification and the stall periods based on the classifying and screening result and splicing the obtained differential values; step (3), dictionary encoding the valid differential slicing data segments recorded in step (2). The present invention effectively combines the architecture compression and non-architecture compression and proposes a three-stage compression scheme by organizing and applying classifying and screening, differential encoding and dictionary compression, which drastically increases the compression ratio of the program counter.

Abstract: The present invention discloses a method for determination of magnesium content in aluminum alloy, including: dissolving an aluminum alloy sample, using one or more compounds selected from the group consisting of mercapto-containing compound, acetone cyanohydrin, ?-aminoethyl mercaptan, triethanolamine, tetraethylenepentamine, ethylene diamine and oxydol as masking agent, using eriochrome black T or methyl thymol blue as indicator, and using EDTA or CDTA to titrate the sample.

Abstract: The present invention discloses a method for determination of magnesium content in aluminum alloy, including: dissolving an aluminum alloy sample, using one or more compounds selected from the group consisting of mercapto-containing compound, acetone cyanohydrin, ?-aminoethyl mercaptan, triethanolamine, tetraethylenepentamine, ethylene diamine and oxydol as masking agent, using eriochrome black T or methyl thymol blue as indicator, and using EDTA or CDTA to titrate the sample.