Abstract: An electronic timepiece includes frequency-dividing circuit means for generating a first signal of at least 1 Hz from a signal of a predetermined frequency. This first signal is counted by a time counter. The frequency-dividing circuit and the time counter are reset in response to the closing of a first input switch. Circuitry is provided for releasing the frequency-dividing circuit from its reset condition to generate a second signal of at least 1 Hz as a quick advance signal for time setting in response to the closing of a second input switch.

Abstract: An arrangement for correcting an electronic timepiece comprises a normally reset flip-flop that holds, when set, a "second" counter in a reset state. When a first switch is closed after being released, the timepiece cyclically gives a normal, a "minute," and an "hour" indication. While a "minute" indication is given, a second switch is closed to set the flip-flop and advance a "minute" counter. When the second switch is released after the "minute" indication is advanced to a correct time, the "second" and "minute" counter are kept still. When the first switch is closed at the correct time after being preliminarily released, the flip-flop is reset to restart the watch with correct "minute" and "second" indications. The arrangement enables the correction to be carried out once again. While given, an "hour" indication is corrected by the second switch.

Abstract: A chattering prevention circuit includes a counter, which upon receiving an input signal including a chattering signal such as from a switch contact, begins to count a clock signal. When the count reaches a predetermined value, a gate signal is generated which, in turn, is employed to gate the input signal. The input signal is delayed by a time corresponding to the period during which the chattering phenomenon remains in effect following the closing of the contact, thereby to prevent chattering.