Patents by Inventor Yukuya Tokumaru
Yukuya Tokumaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 4489247Abstract: An integrated injection logic circuit includes a plurality of integrated injection logic gates each having a PNP transistor for injector and NPN transistor for signal inversion, and an injector common line to which the respective injector PNP transistors are commonly connected. A test pad for electric probing is provided at least one location of the injector common line.Type: GrantFiled: February 17, 1982Date of Patent: December 18, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Masashi Ikeda, Yukuya Tokumaru, Masanori Nakai, Masaki Ota
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Patent number: 4459606Abstract: The integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on the N type semiconductor substrate, a first N type region extending through the P type semiconductor layer to reach the N type semiconductor substrate, a P type region formed in the first N type region and having a periphery along the outer periphery of the first N type region and a second N type region formed in the P type semiconductor layer. The integrated injection logic semiconductor device is constituted by a PNP lateral transistor utilizing the P type region, the first N type region and the P type semiconductor layer as the emitter, base and collector electrodes respectively, and a NPN vertical transistor utilizing the N type semiconductor substrate, P type semiconductor layer and the second N type region as the emitter, base and collector electrodes, respectively.Type: GrantFiled: December 24, 1975Date of Patent: July 10, 1984Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
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Patent number: 4260906Abstract: A semiconductor device comprises a P type semiconductor substrate; an N type layer buried in the P type substrate; and an N type isolating region extending from the surface of the P type substrate to the N type buried region to provide a P type isolated region in the P type substrate. In the P type isolated region marked off by the N type isolating region is formed a first N type region so as not to contact the N type isolating region and buried region and a P type second region is diffused in the first N type region. A logic circuit is constituted by a first vertical PNP transistor formed of the P type second region, first N type region and P type isolated region and a second vertical NPN transistor formed of the first N type region, P type isolated region and N type buried region.Type: GrantFiled: May 15, 1978Date of Patent: April 7, 1981Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai
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Patent number: 4172384Abstract: A measuring apparatus comprises: a first series circuit having first and second resistors connected between a power source terminal and ground; a second series circuit having a thermistor and a third resistor connected between the power source and ground; a first variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the first and second resistors of the first series circuit; a second variable frequency oscillator for generating a pulse signal with the frequency corresponding to the current derived from the junction between the thermistor and the third resistor; a first counter which counts the pulse signal from the second variable frequency oscillator to produce a high level signal till it counts a given number of pulses; and AND gate connected to the output terminal of the first variable frequency oscillator and the first counter, a second counter for counting the pulse fed from the first variable frequency oscillator viaType: GrantFiled: May 24, 1978Date of Patent: October 30, 1979Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Hiroshi Tamura, Masao Kato, Yukuya Tokumaru, Masanori Nakai
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Patent number: 4153487Abstract: A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively.Type: GrantFiled: August 5, 1977Date of Patent: May 8, 1979Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
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Patent number: 4151019Abstract: A P type semiconductor layer is formed on an N type semiconductor layer by vapor epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively.Type: GrantFiled: August 5, 1977Date of Patent: April 24, 1979Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
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Patent number: 4119998Abstract: An integrated injection logic semiconductor device is composed of an N type semiconductor substrate, a P type layer, a first N type region so formed as to penetrate through the P type semiconductor layer and contact the N type semiconductor substrate, a second N type region formed in the P type semiconductor layer, and a P type region formed in the first N type region. A third N type region is provided surrounding said first and second N type regions and penetrating through the P type semiconductor layer. I.sup.2 L circuit is composed of a lateral PNP transistor whose emitter, base and collector are constituted by said P type region, said first N type region and said P type semiconductor layer, respectively, and a vertical NPN transistor whose emitter, base and collector are constituted by said N type semiconductor substrate, said P type semiconductor layer and said second N type region, respectively.Type: GrantFiled: July 14, 1977Date of Patent: October 10, 1978Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
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Patent number: 4110634Abstract: A gate circuit is constituted by a plurality of logical elements formed on the same P type semiconductor substrate. Each logical element is composed of an N type first region and P type second region formed by double diffusion in one of a plurality of P type isolated islands formed on a P type semiconductor substrate, and an N type isolating region and N type buried region surrounding the islands. The P type second region, N type first region and P type island constitute a first vertical PNP transistor by operating as an emitter, base and collector, respectively, while the N type first region, P type island and N type buried region constitute a second vertical NPN transistor by operating as an emitter, base and collector, respectively. In the plurality of logical elements, a Schottky diode is provided for each input section thereof.Type: GrantFiled: August 9, 1976Date of Patent: August 29, 1978Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai
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Patent number: 4091296Abstract: A semiconductor R-S flip-flop circuit comprises first and second input terminals, first and second output terminals, a first integrated injection logic unit consisting of a first transistor acting as a switching element and a second transistor acting as an injector, and a second integrated injection logic unit consisting of a third transistor acting as a switching element and a fourth transistor acting as an injector. The R-S flip-flop circuit further includes a first diode having a cathode connected to the first input terminal and an anode connected to the base of the first transistor, a second diode having a cathode connected to the second input terminal and an anode connected to the base of the third transistor, a third diode having an anode connected to the base of the first transistor and a cathode connected to the collector of the third transistor, and a fourth diode having an anode connected to the base of the third transistor and a cathode connected to the collector of the first transistor.Type: GrantFiled: November 30, 1976Date of Patent: May 23, 1978Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yasoji Suzuki, Yukuya Tokumaru, Masanori Nakai
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Patent number: 4071774Abstract: In the semiconductor device, a P.sup.- conductivity type semiconductor layer is formed on an N.sup.+ conductivity type semiconductor substrate by vapor phase growth technique, and a first N conductivity type region is formed in the P.sup.- conductivity type layer by diffusion to extend into the N.sup.+ conductivity type substrate and to surround a portion of the P.sup.- conductivity type semiconductor layer thereby isolating that portion from the remainder. A second conductivity type region is formed in the first region by diffusion and a third N conductivity type region is formed on the isolated region of the P.sup.- conductivity type layer. At least one metal region is bonded to the isolated region and at least one metal region is bonded to the third region to form respective metal-semiconductor contact diodes. The second region, the first region and the P.sup.- conductivity type layer constitute a lateral PNP transistor while the third region, the P.sup.- conductivity type semiconductor layer and the N.Type: GrantFiled: December 24, 1975Date of Patent: January 31, 1978Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai
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Patent number: 4065187Abstract: A semiconductor latch circuit formed of a plurality of integrated injection logic (abbreviated as "IIL") units each comprising a switching transistor acting as a switching element and an injector transistor acting as an injector, wherein a Schottky diode is connected to the base of the switching transistor.Type: GrantFiled: November 30, 1976Date of Patent: December 27, 1977Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yasoji Suzuki, Yukuya Tokumaru, Masanori Nakai
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Patent number: 4064526Abstract: An integrated injection logic semiconductor device comprises an N type semiconductor substrate, a P type semiconductor layer laminated on said semiconductor substrate, and N type first region formed in a manner penetrating through said P type semiconductor layer to reach said N type semiconductor substrate, a first P type region formed in said first N type region, a second N type regionformed in said P type semiconductor layer, and a second P type region formed between said second N type region and said N type semiconductor substrate in a manner connected directly to said N type semiconductor substrate.Type: GrantFiled: December 24, 1975Date of Patent: December 20, 1977Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
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Patent number: 4058419Abstract: A P type semiconductor layer is formed on an N type semiconductor layer by vapour epitaxial growth technique, an insulating film is formed on the P type semiconductor layer and a grid shape first opening is provided through the insulating film. Then, phosphorus is diffused into the P type semiconductor layer through the grid shape opening to form a first N type region extending through the semiconductor layer to reach the N type semiconductor layer. Then, second openings are formed through respective sections of the insulating film divided by and surrounded by the grid shape first opening and boron is diffused through the first and second openings to form first and second P type regions in the grid shape first N type region and the P type semiconductor layer, respectively.Type: GrantFiled: December 24, 1975Date of Patent: November 15, 1977Assignee: Tokyo Shibaura Electric, Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi
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Patent number: 4054900Abstract: An integrated injection logic semiconductor device which comprises an N type semiconductor substrate; a P type semiconductor layer superposed on the N type semiconductor substrate; a first N type region formed in the P type semiconductor layer; a second N type region formed in the P type semiconductor layer; and a P type region formed in the first N type region, wherein the first N type region is connected to the N type semiconductor substrate through an N type connector region formed between the first N type region and N type semiconductor substrate.Type: GrantFiled: December 24, 1975Date of Patent: October 18, 1977Assignee: Tokyo Shibaura Electric Co., Ltd.Inventors: Yukuya Tokumaru, Masanori Nakai, Satoshi Shinozaki, Junichi Nakamura, Shintaro Ito, Yoshio Nishi