Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.

Abstract: A memory system including: a memory module including a plurality of memory chips; a mirror memory module including a plurality of mirror memory chips corresponding to the plurality of memory chips, a first mirror memory chip of the plurality of mirror memory chips being storing same data as a first memory chip of the plurality of memory chips; and a memory controller configured to, in a system running state in which an operation according to a request of a user is capable of being performed after the memory system is booted, provide the memory module with a command for instructing a normal operation to be performed and provide the mirror memory module with a command for instructing a memory built-in self-test (MBIST) to be performed.

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.