Abstract: Aspects described herein relate to physical verification of a design of an integrated circuit to be manufactured on a semiconductor die. One example method involves inserting a virtual partition cell in a parent cell of a layout of a design of an integrated circuit. A child cell of the parent cell has a first portion that overlaps the virtual partition cell and a second portion that is outside of the virtual partition cell. The method also includes creating, by one or more processors, a hierarchy of cells having the child cell and the virtual partition cell descending from the parent cell, wherein the child cell has multiple instances in the hierarchy of cells, and performing a design rule check runset on the parent cell based on the hierarchy.

Abstract: Aspects described herein relate to physical verification of a design of an integrated circuit to be manufactured on a semiconductor die. One example method involves inserting a virtual partition cell in a parent cell of a layout of a design of an integrated circuit. A child cell of the parent cell has a first portion that overlaps the virtual partition cell and a second portion that is outside of the virtual partition cell. The method also includes creating, by one or more processors, a hierarchy of cells having the child cell and the virtual partition cell descending from the parent cell, wherein the child cell has multiple instances in the hierarchy of cells, and performing a design rule check runset on the parent cell based on the hierarchy.

Abstract: The present invention provides a compound comprising a 5-membered heterocycle fused with a pyridazinone, wherein the compound is used as an FGFR kinase inhibitor, and a manufacturing method and application thereof. The invention specifically provides a compound as represented by formula (I). Various radicals are as defined in the specification. The compound provided by the invention effectively inhibits an activity of an FGFR kinase, and can be used to manufacture a pharmaceutical product for treating a disease related to the activity of the FGFR kinase.

Abstract: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

Abstract: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

Abstract: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

Abstract: A novel oxyfullerene hollow nanosphere of CxOyMnz (45?x?72, 18?y?42, 7?z?16; x, y and z are atomic percentages) has a large surface area and high thermal stability, and can be simply prepared by reacting fullerene with alkali metal hydroxide and KMnO4 or MnO2, and treating the resulting mixture with an acid.

Abstract: Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A trim region within each projection region is defined using the associated detection circle, such that a portion of the trim region boundary exhibits tangency to the detection circle. The trim regions, which represent non-wide portions of the layout, are then removed to generate a wide element layout. Because the detection circle is a rotation-independent geometry, the over-extraction and under-extraction problems associated with conventional wide element extraction methods can be eliminated.

Abstract: When performing rule checking locally within any given region of a layout of an integrated circuit, certain data is generated to be checked globally, regardless of boundaries (hereinafter “to-be-globally-checked” data). The to-be-globally-checked data, resulting from execution of a given rule in each region of the IC layout, is merged across all regions, and the same rule (i.e. the given rule) is executed globally on the merged data. When an entire runset has been executed in all regions individually, and also executed globally on the merged data, the results thereof are all merged together to yield a final result of a complete execution of the entire runset over the entire IC layout. In some embodiments, certain additional data that could not be rule checked due to the presence of boundaries of adjacent regions is propagated between successive rules in each region.

Abstract: Wide geometry can be accurately extracted from the physical layout of an integrated circuit through the use of detection circles having diameters equal to a threshold width. Projection regions in the layout are selected, and for each projection region, a detection circle of a threshold width (diameter) is defined. A trim region within each projection region is defined using the associated detection circle, such that a portion of the trim region boundary exhibits tangency to the detection circle. The trim regions, which represent non-wide portions of the layout, are then removed to generate a wide element layout. Because the detection circle is a rotation-independent geometry, the over-extraction and under-extraction problems associated with conventional wide element extraction methods can be eliminated.

Abstract: Fullerenols having a nanolayer or a nanowire structure are prepared under a mild condition with high efficiency by reacting fullerene with an alkali metal hydroxide dissolved in water.

Abstract: A novel oxyfullerene hollow nanosphere of CxOyMnz (45?x?72, 18?y?42, 7?z?16; x, y and z are atomic percentages) has a large surface area and high thermal stability, and can be simply prepared by reacting fullerene with alkali metal hydroxide and KMnO4 or MnO2, and treating the resulting mixture with an acid.

Abstract: A robotics-control processor for performing real-time inverse kinematics and inverse dynamics calculations involving three-dimensional vectors. The processor employs a three-wide register and execution unit architecture, pipelined instructions, and register-to-register data processing to achieve rapid vector calculations. Broadcast buffers for exchanging operands between register files, and operand multiplexing at several levels within the processor allow program operation flexibility. In a preferred embodiment, the processor includes a CORDIC algorithm unit for rapid vector rotation and trigonometric function calculations.