Abstract: An operation accelerator for processing an operation between floating-point data and integer data includes a data converter configured to receive one of the integer data and the floating-point data as first input data and to output integer operation target data; a data setting unit configured to divide the integer operation target data into units of a same size and to transmit the integer operation target data to an arithmetic unit; the arithmetic unit configured to perform a multiply and accumulation (MAC) operation on second input data received as an integer and the integer operation target data received from the data setting unit; and a merger configured to adjust an operation result of the arithmetic unit by compensating for an original scale omitted in a process of dividing the integer operation target data into the units of the same size.

Abstract: An operation accelerator that performs an operation between a floating point matrix and an integer matrix includes a first buffer storing integer matrix data; a second buffer storing floating point matrix data; a data converter to convert the floating point matrix data into an integer; and an operator to perform multiplication on the integer matrix data and integer operation target matrix data output from the data converter, wherein the data converter includes a pre-aligner to find a maximum exponent value among multiple floating point values included in the floating point matrix data, perform pre-alignment for moving a mantissa of each of floating points by a difference between the maximum exponent value and an exponent value of each of the multiple floating point values, and generate the integer operation target matrix data based on mantissas of a preset number of high-order bits extracted from among mantissas of pre-aligned floating point values.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: An electronic system may include: a camera to capture a current image; an image processor to generate current image data items; and a splitter circuit to generate first and second images having respective first and second image data items. The splitter circuit splits each current image data item into a first image data item with a first set of bits and a second image data item with a second set of bits distinct from the first set of bits. The first and second image data items correspond to two distinct precisions less than a precision of the current image data items. The electronic system may also include distinct binary neural network circuits to independently process the first and second images to generate first and second processed image data items; and a merger circuit to combine the processed image data items to recover output image data items for display.

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Abstract: Disclosed are a first memory cell, a second memory cell, and a summing circuit. The first memory cell outputs only one of a first voltage through a first bit line and a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs only one of a third voltage through the first bit line and a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight; and the summing circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Abstract: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Disclosed are a first memory cell, a second memory cell, and an amplification circuit. The first memory cell outputs a first voltage through a first bit line or a second voltage through a second bit line, based on first input data received through a first word line and a second word line and a first weight. The second memory cell outputs a third voltage through the first bit line or a fourth voltage through the second bit line, based on second input data received through a third word line and a fourth word line and a second weight. The amplification circuit generates an output voltage having a level corresponding to a sum of a level of a voltage received through the first bit line and a level of a voltage received through the second bit line.

Abstract: Disclosed is a method of operating a neural network system. The method includes splitting input feature data into first splitting data corresponding to a first digit bit and second splitting data corresponding to a second digit bit different from the first digit bit, propagating the first splitting data through a first binary neural network, propagating the second splitting data through a second binary neural network, and merging first result data by propagation of the first splitting data and second result data by propagating the second splitting data to generate output feature data.

Abstract: A method of implementing a neural network in a neuromorphic apparatus having a memory and processing circuitry, where the method includes dividing, by the processing circuitry, the neural network into a plurality of sub-networks based on a size of a core of the memory to implement the neural network, initializing, by the processing circuitry, a hyper-parameter used in the sub-networks, and training, by the processing circuitry, the sub-networks by using the hyper-parameter.

Abstract: Provided is an artificial neural network circuit including unit weight memory cells including weight memory devices configured to store weight data and weight pass transistors, unit threshold memory cells including a threshold memory device programmed to store a threshold and a threshold pass transistor, a weight-threshold column in which the plurality of unit weight memory cells and the plurality of unit threshold memory cells are connected, and a sense amplifier configured to receive an output signal of the weight-threshold column as an input and receive a reference voltage as another input.

Abstract: A method of performing operations on a plurality of inputs and a same kernel using a delay time by using a same processor, and a neural network device thereof are provided, the neural network device includes input data including a first input and a second input, and a processor configured to obtain a first result by performing operations between the first input and a plurality of kernels, to obtain a second result by performing operations between the second input, which is received at a time delayed by a first interval from a time when the first input is received, and the plurality of kernels, and to obtain output data using the first result and the second result. The neural network device may include neuromorphic hardware and may perform convolutional neural network (CNN) mapping.