Abstract: One embodiment provides a power semiconductor device that includes a semiconductor body. A source region of a first conductivity type is disposed at a top side the semiconductor body. A channel region of a second conductivity type is disposed in the semiconductor body below the source region and a drift region of the first conductivity type is disposed in the semiconductor body below the channel region. A trench extends from the top side through the source region and through the channel region and ending in the drift region. As seen in a top view of the top side, the trench comprises a plurality of branch-offs. A gate electrode is disposed within the trench and a shield region of the second conductivity type is located at least partially below a branch-off of the trench.

Abstract: A power semiconductor device and method for production thereof is specified involving an electrode, a base layer of a first conductivity type provided on the electrode, at least one contact layer provided on the base layer, a gate contact provided on the base layer and on the at least one contact layer, an insulation layer between the gate contact and the base layer and between the at least one contact layer and the gate contact, and at least one zone of a second conductivity type within the base layer, wherein the at least one zone is constructed and arranged to shift away a peak electric field generated in the base layer from the insulation layer between the gate contact and the base layer.

Abstract: In at least one embodiment, the power semiconductor device 1) involves a semiconductor body (2), at least one source region (21) in the semiconductor body (2), a gate electrode (3) at the semiconductor body (2), a gate insulator (4, 41, 42) between the semiconductor body (2) and the gate electrode (3), and at least one well region (22) at the at least one source region (21) and at the gate insulator (4, 41, 42), wherein the gate insulator (4, 41, 42) has a varying dielectric capacitance, the dielectric capacitance is in each case a quotient of a dielectric constant and of a geometric thickness of the gate insulator (4, 41, 42) at a specific location thereof, and the dielectric capacitance is larger at the at least one well region (22) than in remaining regions of the gate insulator (4, 42).