Patents by Inventor Yulin CUI

Yulin CUI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127885
    Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.
    Type: Grant
    Filed: March 22, 2020
    Date of Patent: September 21, 2021
    Assignees: Ordos Yuansheng Optoelectronics Co., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Hong Liu, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
  • Publication number: 20210159364
    Abstract: Disclosed are an array substrate, a display panel and a display device. The array substrate includes: a base substrate provided with a bonding region for packaging a chip on film, and a first electrode structure, an interlayer dielectric layer, a second electrode structure and a third electrode structure sequentially arranged on the base substrate, the orthographic projections of the first electrode structure, the interlayer dielectric layer, the second electrode structure and the third electrode structure on the base substrate being located in the bonding region. The array substrate further includes protection layers located between the first portion of the second electrode structure and a third electrode and between the second portion of the second electrode structure and the third electrode respectively; and the protection layers cover the side end face of the first portion and the side end face of the second end surface.
    Type: Application
    Filed: March 22, 2020
    Publication date: May 27, 2021
    Inventors: Hong LIU, Yezhou Fang, Fengguo Wang, Xinguo Wu, Zhixuan Guo, Haidong Wang, Liang Tian, Dong Zhang, Yue Yang, Yulin Cui
  • Patent number: 9825063
    Abstract: The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 21, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jing Li, Yulin Cui
  • Publication number: 20160372489
    Abstract: The present invention provides a display panel, a fabricating method thereof and a display device. The display panel comprises a pixel region and a fan-out region, first signal lines and second signal lines are provided to intersect each other in the pixel region, and extend into the fan-out region, respectively, a first insulation layer is provided between the first signal lines and the second signal lines, a second insulation layer is provided on the second signal lines, the second insulation layer comprises at least four layers of structures, and a density of each layer of structure of the second insulation layer decreases gradually along a direction away from the first insulation layer. A size of the via hole formed in the second insulation layer by etching is smaller than that of the via hole formed in the prior art.
    Type: Application
    Filed: August 18, 2015
    Publication date: December 22, 2016
    Inventors: Jing LI, Yulin CUI