Abstract: Disclosed are adenosine deaminases, base editors comprising the adenosine deaminases and complexes comprising the base editors. The adenosine deaminases and the base editors exhibited superior adenine editing effects and achieved A·T base pair to G·C base pair transformation at DNA level.

Abstract: Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.

Abstract: Disclosed are an audio ADC for supporting voice wake-up and an electronic device. The audio ADC includes a programmable gain amplifier (PGA) having an input terminal for receiving an audio signal; a bypass switch having an input terminal for receiving an analog audio signal; and a successive approximation ADC having input terminals respectively connected to output terminals of the PGA and the bypass switch; the PGA gains and amplifies the audio signal, the bypass switch bypasses the PGA, and outputs the analog audio signal; the successive approximation performs analog-to-digital conversion with noise shaping on the analog audio signal after gain amplification at a first sampling rate/oversampling rate when the audio ADC is normal working, and turns off noise shaping when the audio ADC is sleep, performs analog-to-digital conversion on the analog audio signal output by the bypass switch at a second sampling rate/oversampling rate, and outputs to a DSP.

Abstract: Disclosed are a pre-drive module of an analog-to-digital converter and an analog-to-digital conversion device. The pre-drive module includes a sampling capacitor; a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence; a reset module configured to reset the sampling capacitor upon receiving the reset control signal; a first auxiliary drive circuit configured to amplify an input analog signal and output to the sampling capacitor for sampling upon receiving the sample control signal; and a second auxiliary drive circuit. The controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output to the sampling capacitor for pre-sampling, and when a charging voltage of the sampling capacitor during pre-sampling reaches a preset voltage value, output the sampling control signal.

Abstract: Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

Abstract: A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.

Abstract: A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

Abstract: Disclosed are an audio ADC for supporting voice wake-up and an electronic device. The audio ADC includes a programmable gain amplifier (PGA) having an input terminal for receiving an audio signal; a bypass switch having an input terminal for receiving an analog audio signal; and a successive approximation ADC having input terminals respectively connected to output terminals of the PGA and the bypass switch; the PGA gains and amplifies the audio signal, the bypass switch bypasses the PGA, and outputs the analog audio signal; the successive approximation performs analog-to-digital conversion with noise shaping on the analog audio signal after gain amplification at a first sampling rate/oversampling rate when the audio ADC is normal working, and turns off noise shaping when the audio ADC is sleep, performs analog-to-digital conversion on the analog audio signal output by the bypass switch at a second sampling rate/oversampling rate, and outputs to a DSP.

Abstract: Disclosed are a pre-drive module of an analog-to-digital converter and an analog-to-digital conversion device. The pre-drive module includes a sampling capacitor; a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence; a reset module configured to reset the sampling capacitor upon receiving the reset control signal; a first auxiliary drive circuit configured to amplify an input analog signal and output to the sampling capacitor for sampling upon receiving the sample control signal; and a second auxiliary drive circuit. The controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output to the sampling capacitor for pre-sampling, and when a charging voltage of the sampling capacitor during pre-sampling reaches a preset voltage value, output the sampling control signal.

Abstract: Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.

Abstract: Disclosed are an audio rate conversion system and an electronic apparatus. The audio rate conversion system includes an integrator-comb filter, a multi-rate filter and a first half-band filter, an input of the integrator-comb filter being accessed with digital audio data, an output of the integrator-comb filter being sequentially connected to the multi-rate filter and the first half-band filter; where, the integrator-comb filter is configured to reduce a rate of the digital audio data according to a preset decimation rate; the multi-rate filter is configured to convert a rate of digital audio data output by the integrator-comb filter into a rate of digital audio data corresponding to an accessed control signal according to the control signal; and the first half-band filter is configured to reduce a rate of digital audio data output by the multi-rate filter.

Abstract: Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

Abstract: A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

Abstract: A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.

Abstract: The present disclosure provides a signal calibration method, apparatus and device generated based on an imbalance of I path and Q path. The method includes sending a cosine signal and a sine signal through a signal generator, transmitting the cosine signal and the sine signal in the I path and the Q path respectively, the cosine signal and the sine signal being configured to loop back to a signal receiving direction after passing through a transmitting amplifier; processing a signal obtained by a down converter in the signal receiving direction; performing a phase adjustment and an amplitude adjustment by adjusting the signal generator, gain amplifiers of I path and Q path analog domains, and a corresponding digital domain, so as to determine an appropriate phase cancellation value and an appropriate amplitude cancellation value for an image signal; and calibrating the image signal corresponding to the signal to be calibrated.

Abstract: The present application discloses a filtering method and a filtering device of a filter, a filter and a storage medium. The method includes: obtaining a clock input signal and a clock output signal and comparing them, and determining a phase relationship between the clock input signal and the clock output signal according to a comparison result; determining a decimal deviation factor according to the phase relationship in determining that the phase relationship meets a preset condition; and filtering a sample input signal according to the decimal deviation factor to obtain a filtered sample output signal. The present application can obtain an accurate decimal deviation factor, by obtaining the phase relationship between the clock input signal and the clock output signal, in determining that the phase relationship meets a preset condition, and can adjust the sample input signal according to the decimal deviation factor to obtain a smooth sample output signal.

Abstract: The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.

Abstract: The present disclosure provides a method for compensating an imbalance between an I path and a Q path of a receiver. The method includes: sending a cosine signal and a sine signal through a signal generator, transmitting the cosine signal and the sine signal in the I path and Q path respectively; calculating autocorrelation values of the I path and the Q path in the signal receiving direction; determining a comparison result of amplitudes of the cosine signal received by the I path and the sine signal received by the Q path according to the autocorrelation values; calculating an adjustment compensation value of an analog domain gain amplifier, and an amplitude value and a phase value in a digital domain according to the comparison result of amplitudes; and compensating and adjusting the signal according to the adjustment compensation value, the amplitude value and the phase value.

Abstract: The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2N?1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital

Abstract: The present disclosure provides a dual-edge triggered ring buffer and a communication system. The dual-edge triggered ring buffer includes a logic clock generation module and a data writing module. The logic clock generation module is configured to generate a corresponding first logic clock signal upon detecting an input of the trigger signal corresponding to the multiple first trigger signal input terminals, or to generate a corresponding second logic clock signal upon detecting an input of the trigger signal corresponding to the multiple second trigger signal input terminals. The data writing module is configured to write data output from the external system through the multiple corresponding input terminals according to the first logic clock signal or the second logic clock signal.