Abstract: The present disclosure relates to a logic operation circuit for computation in memory, which comprises an equivalent circuit input terminal, a reference circuit input terminal, a reset input terminal and an output terminal; wherein the equivalent circuit input terminal is configured to input the equivalent voltage of a memory computing array, the reset input terminal is configured to input a reset voltage, and the reference circuit input terminal is configured to input a reference voltage; the logic operation circuit for computation in memory outputs different output voltages according to the difference between the equivalent voltage and the reference voltage, and the output voltage is output through the output terminal; the logic operation circuit of the present disclosure has a simple structure, reduced complexity and effectively saved resources.

Abstract: This document relates to methods and materials involved in treating cancer. For example, methods and materials for using one or more oncolytic viruses (e.g., one or more replicating oncolytic viruses) to treat cancer in a mammal (e.g., a human) identified as having a cancer likely to respond to oncolytic virotherapy are provided.

Abstract: This document relates to methods and materials involved in treating cancer. For example, methods and materials for using one or more oncolytic viruses (e.g., one or more replicating oncolytic viruses) to treat cancer in a mammal (e.g., a human) identified as having a cancer likely to respond to oncolytic virotherapy are provided.

Abstract: The present disclosure relates to a logic operation circuit for computation in memory, which comprises an equivalent circuit input terminal, a reference circuit input terminal, a reset input terminal and an output terminal; wherein the equivalent circuit input terminal is configured to input the equivalent voltage of a memory computing array, the reset input terminal is configured to input a reset voltage, and the reference circuit input terminal is configured to input a reference voltage; the logic operation circuit for computation in memory outputs different output voltages according to the difference between the equivalent voltage and the reference voltage, and the output voltage is output through the output terminal; the logic operation circuit of the present disclosure has a simple structure, reduced complexity and effectively saved resources.

Abstract: The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal.

Abstract: The present disclosure provides a serial PWM signal decoding circuit based on a capacitor charge-discharge structure, comprising: a timing logic generation circuit configured to receive, at an input end of the timing logic generation circuit, a PWM differential signal, and generate a timing logic signal; and at least two capacitor charge-discharge decoding modules, each of the at least two capacitor charge-discharge decoding modules has an input end connected to an output end of the timing logic generation circuit, and is configured to perform charging and discharging based on the timing logic signal.

Abstract: This document relates to methods and materials involved in treating cancer. For example, methods and materials for using one or more oncolytic viruses (e.g., one or more replicating oncolytic viruses) to treat cancer in a mammal (e.g., a human) identified as having a cancer likely to respond to oncolytic virotherapy are provided.