Patents by Inventor Yumi TAKADA

Yumi TAKADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10847232
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
  • Publication number: 20200295742
    Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.
    Type: Application
    Filed: September 10, 2019
    Publication date: September 17, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Yousuke HAGIWARA, Kenta SHIBASAKI, Yumi TAKADA
  • Publication number: 20200202959
    Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.
    Type: Application
    Filed: August 29, 2019
    Publication date: June 25, 2020
    Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
  • Publication number: 20200185044
    Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.
    Type: Application
    Filed: August 30, 2019
    Publication date: June 11, 2020
    Inventors: Yumi TAKADA, Yasuhiro HIRASHIMA, Kenta SHIBASAKI, Yousuke HAGIWARA
  • Patent number: 10593405
    Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryuichi Fujimoto, Kan Shimizu, Shigehito Saigusa, Motoki Nagata, Yumi Takada, Hitoshi Shiga, Makoto Morimoto
  • Publication number: 20190335093
    Abstract: An image sensor comprising a pixel portion that is constituted by a plurality of pixels, and includes a first pixel group and a second pixel group, wherein each of the pixels included in the first pixel group and the second pixel group includes: a plurality of photoelectric conversion portions; and a plurality of transfer gates that respectively correspond to the photoelectric conversion portions, and have transfer gate electrodes covering same partial regions in the photoelectric conversion portions, and an average position of barycenters of respective light receivable regions of the photoelectric conversion portions included in each pixel of the first pixel group and an average position of barycenters of respective light receivable regions of the photoelectric conversion portions included in each pixel of the second pixel group are at positions different from each other in the pixels.
    Type: Application
    Filed: July 12, 2019
    Publication date: October 31, 2019
    Inventors: Koichi Fukuda, Junichi Saito, Yumi Takao, Yoshiaki Takada, Masaaki Iwane, Shoji Kono
  • Publication number: 20190295649
    Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.
    Type: Application
    Filed: August 13, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Ryuichi FUJIMOTO, Kan SHIMIZU, Shigehito SAIGUSA, Motoki NAGATA, Yumi TAKADA, Hitoshi SHIGA, Makoto MORIMOTO
  • Patent number: 10404905
    Abstract: An image sensor comprising a pixel portion that is constituted by a plurality of pixels, and includes a first pixel group and a second pixel group, wherein each of the pixels included in the first pixel group and the second pixel group includes: a plurality of photoelectric conversion portions; and a plurality of transfer gates that respectively correspond to the photoelectric conversion portions, and have transfer gate electrodes covering same partial regions in the photoelectric conversion portions, and an average position of barycenters of respective light receivable regions of the photoelectric conversion portions included in each pixel of the first pixel group and an average position of barycenters of respective light receivable regions of the photoelectric conversion portions included in each pixel of the second pixel group are at positions different from each other in the pixels.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: September 3, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Fukuda, Junichi Saito, Yumi Takao, Yoshiaki Takada, Masaaki Iwane, Shoji Kono
  • Patent number: 10298867
    Abstract: The imaging device includes a first pixel group and a second pixel group that include a plurality of pixels each having a plurality of photoelectric conversion portions that are separated by an isolation portion and arranged in a first direction and a plurality of transfer gates that transfer charges of the plurality of photoelectric conversion portions. A position of at least a part of the isolation portion within each of the pixels of the first pixel group and a position of at least a part of the isolation portion within each of the pixels of the second pixel group are shifted relative to each other in the first direction. Respective widths of portions where the plurality of separated photoelectric conversion portions overlap with the plurality of transfer gates in a planar view are the same.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 21, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshiaki Takada, Masaaki Iwane, Shoji Kono, Koichi Fukuda, Junichi Saito, Yumi Takao