Patents by Inventor Yumi TAKADA
Yumi TAKADA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11456023Abstract: There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.Type: GrantFiled: December 14, 2020Date of Patent: September 27, 2022Assignee: Kioxia CorporationInventors: Yutaka Shimizu, Satoshi Inoue, Isao Fujisawa, Yumi Takada
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Publication number: 20210335401Abstract: According to one embodiment, there is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.Type: ApplicationFiled: December 14, 2020Publication date: October 28, 2021Applicant: Kioxia CorporationInventors: Yutaka SHIMIZU, Satoshi INOUE, Isao FUJISAWA, Yumi TAKADA
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Patent number: 11087852Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.Type: GrantFiled: August 30, 2019Date of Patent: August 10, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yumi Takada, Yasuhiro Hirashima, Kenta Shibasaki, Yousuke Hagiwara
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Patent number: 10884674Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.Type: GrantFiled: September 10, 2019Date of Patent: January 5, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yousuke Hagiwara, Kenta Shibasaki, Yumi Takada
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Patent number: 10847232Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: GrantFiled: August 29, 2019Date of Patent: November 24, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kei Shiraishi, Masaru Koyanagi, Mikihiko Ito, Yumi Takada, Yasuhiro Hirashima, Satoshi Inoue, Kensuke Yamamoto, Shouichi Ozaki, Taichi Wakui, Fumiya Watanabe
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Publication number: 20200295742Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, first to third circuits. The first circuit is configured to control duty cycles of first and second signals based on a third signal, and output fourth and fifth signals. The second circuit is configured to acquire information regarding duty cycles. The third circuit is configured to control the third signal. The second circuit includes a switching circuit and a comparator. The switching circuit is configured to transfer the fourth and fifth signals to first and second nodes. The comparator is configured to compare a signal voltages in the first and second nodes, and output the comparison result to the third circuit.Type: ApplicationFiled: September 10, 2019Publication date: September 17, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yousuke HAGIWARA, Kenta SHIBASAKI, Yumi TAKADA
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Publication number: 20200202959Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.Type: ApplicationFiled: August 29, 2019Publication date: June 25, 2020Inventors: Kei SHIRAISHI, Masaru KOYANAGI, Mikihiko ITO, Yumi TAKADA, Yasuhiro HIRASHIMA, Satoshi INOUE, Kensuke YAMAMOTO, Shouichi OZAKI, Taichi WAKUI, Fumiya WATANABE
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Publication number: 20200185044Abstract: A semiconductor storage device includes a first chip and a second chip. In response to a first command that is received on a first terminal of the first chip and a second terminal of the second chip that are connected to a command signal line, the first chip and the second chip execute in parallel a first correction process of correcting a duty cycle of a first output signal generated by the first chip and a second correction process of correcting a duty cycle of a second output signal generated by the second chip, respectively, according a common toggle signal.Type: ApplicationFiled: August 30, 2019Publication date: June 11, 2020Inventors: Yumi TAKADA, Yasuhiro HIRASHIMA, Kenta SHIBASAKI, Yousuke HAGIWARA
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Patent number: 10593405Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.Type: GrantFiled: August 13, 2018Date of Patent: March 17, 2020Assignee: Toshiba Memory CorporationInventors: Ryuichi Fujimoto, Kan Shimizu, Shigehito Saigusa, Motoki Nagata, Yumi Takada, Hitoshi Shiga, Makoto Morimoto
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Publication number: 20190295649Abstract: According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.Type: ApplicationFiled: August 13, 2018Publication date: September 26, 2019Applicant: Toshiba Memory CorporationInventors: Ryuichi FUJIMOTO, Kan SHIMIZU, Shigehito SAIGUSA, Motoki NAGATA, Yumi TAKADA, Hitoshi SHIGA, Makoto MORIMOTO