Patents by Inventor Yumiko Akaishi

Yumiko Akaishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6897525
    Abstract: In order to improve the characteristics of the high breakdown voltage MOS, a semiconductor device of the present invention is characterized in that an LDMOS transistor, which comprises a source region 4, a channel region 8, and a drain region 5, and a gate electrode 7 formed on the channel region 8, and a drift region formed between the channel region 8 and the drain region 5, wherein an N?-type low concentration layer 22 serving as the drift region is formed shallowly at least below the gate electrode 7 (first N?-type layer 22A) but formed deeply in a neighborhood of the drain region 5 (second N?-type layer 22B).
    Type: Grant
    Filed: November 22, 1999
    Date of Patent: May 24, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Yumiko Akaishi
  • Patent number: 6614075
    Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: September 2, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
  • Patent number: 6599782
    Abstract: To enhance the withstand voltage of an LD MOS transistor, a method of fabricating a semiconductor device according to the invention is characterized in that a process for forming a drift region is composed of a step for implanting phosphorus ions and arsenic ions different in a diffusion coefficient into the superficial layer of a substrate, a step for forming a selective oxide film (a first gate insulating film) 9A and an element isolation film 9B by selective oxidation and diffusing the phosphorus ions and the arsenic ions and a step for implanting and diffusing boron ions, and in that in the step for forming the selective oxide film 9A and the element isolation film 9B by selective oxidation in a state in which an oxide film and a polycrystalline silicon film are laminated on the substrate, only a drift region formation region is selectively oxidized in a state in which the polycrystalline silicon film is removed.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: July 29, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Shuichi Kikuchi, Yumiko Akaishi, Takuya Suzuki
  • Publication number: 20010025987
    Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N−layer 22A) and deep in the vicinity of the drain region 5 (second N−layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.
    Type: Application
    Filed: May 10, 2001
    Publication date: October 4, 2001
    Applicant: Sanyo Electric Co., Ltd., a Japan Corporation
    Inventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
  • Patent number: 6255154
    Abstract: A semiconductor device includes a source region 4, a channel region 8, a drain region 5 and a gate electrode which is patterned so that its side wall is tapered to be more narrow toward the top. A drift region 22 is formed between the channel region 8 and drain region 5 so as to be shallow below the gate electrode 7A (first N− layer 22A) and deep in the vicinity of the drain region 5 (second N− layer 22B). This configuration contributes to boosting the withstand voltage and reducing the “on” resistance of the semiconductor device.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: July 3, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yumiko Akaishi, Takuya Suzuki, Shinya Mori, Yuji Tsukada, Yuichi Watanabe, Shuichi Kikuchi
  • Patent number: 6207518
    Abstract: Disclosed is a method of manufacturing a semiconductor device which includes a source region, a channel region, a drain region, a gate electrode formed on the channel region through a gate insulating film 6 and a drift region (N− layer 22) formed between the channel region and the drain region, wherein the process of forming the drift region (N− layer) comprises the steps of: ion-implanting and diffusing at least two kinds of second conduction type impurities (e.g. phosphorus and arsenic ions) having different diffusion coefficients in a P-type well region 21; ion-implanting at least one kind first conduction type impurities (e.g. boron ions) having a diffusion coefficient substantially equal to or larger than that of at least one of said second conduction type impurities (e.g. phosphorus); and diffusing the first conduction type impurities after the gate insulating film 6 has been formed.
    Type: Grant
    Filed: February 24, 2000
    Date of Patent: March 27, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yumiko Akaishi, Shuichi Kikuchi