Patents by Inventor Yumiko Mito

Yumiko Mito has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7502077
    Abstract: A video signal-processing device that can improve the apparent contrast of the luminance signal at a television receiving set includes a quantity of black expansion computing section for computationally determining the quantity of black expansion when the luminance component of the input video signal is not higher than a first luminance level, a gain controller for regulating the quantity of black expansion as computationally determined by the quantity of black expansion computing section, a quantity of black expansion adding section for generating an output video signal by adding the quantity of black expansion regulated by the gain controller to the luminance component of the input video signal, and a vertical span adding block for integrating the luminance component of the output video signal not higher than a second luminance level for a field.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: March 10, 2009
    Assignee: Sony Corporation
    Inventors: Satoshi Miura, Takatomo Nagamine, Yumiko Mito, Jun Ueshima
  • Publication number: 20050157212
    Abstract: A video signal-processing device that can improve the apparent contrast of the luminance signal at a television receiving set includes a quantity of black expansion computing section for computationally determining the quantity of black expansion when the luminance component of the input video signal is not higher than a first luminance level, a gain controller for regulating the quantity of black expansion as computationally determined by the quantity of black expansion computing section, a quantity of black expansion adding section for generating an output video signal by adding the quantity of black expansion regulated by the gain controller to the luminance component of the input video signals and a vertical span adding block for integrating the luminance component of the output video signal not higher than a second luminance level for a field.
    Type: Application
    Filed: June 24, 2003
    Publication date: July 21, 2005
    Inventors: Satoshi Miura, Takatomo Nagamine, Yumiko Mito, Jun Ueshima
  • Patent number: 5455634
    Abstract: A dark level restoring circuit for a television receiver which receives a video signal, clamps a pedestal portion of the video signal to a reference pedestal level by a pedestal clamper, compares the output of the pedestal clamper with a reference dark level, and amplifies the compared result by a gain control amplifier. The output of the pedestal clamper and the amplified compared result are synthesized, the dark peak level is held, and the held dark peak level and the reference pedestal level are compared wherein the gain of the gain control amplifier is controlled by the compared result. A blanking signal is received, and a mute signal is generated which corresponds to a non-video signal portion when the effective raster size of the video signal is smaller than the size of a face plate of a cathode ray tube to which the video signal is supplied.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: October 3, 1995
    Assignee: Sony Corporation
    Inventors: Takahiko Tamura, Yumiko Mito
  • Patent number: 5291287
    Abstract: A vertical synchronization processing circuit includes a counter for counting a clock signal synchronized with a horizontal sync. signal, a circuit for resetting the counter in response to a vertical synchronization signal within a predetermined limit prohibiting reset due to a non-standard signal, a memory for storing the data counted at the timing of reset, and a circuit for changing a predetermined limit prohibiting reset due to a non-standard signal according to the data from the memory. A circuit for discriminating an existence of a vertical synchronization interval can also be provided along with a second resetting circuit for resetting the counter if the discriminating circuit detects the existence of the vertical synchronization interval when the counter counts a predetermined number of clock signals in case there is not a vertical synchronization pulse within the predetermined limit.
    Type: Grant
    Filed: May 27, 1992
    Date of Patent: March 1, 1994
    Assignee: Sony Corporation
    Inventors: Hiroshi Murayama, Akira Shirahama, Takahiko Tamura, Yumiko Mito, Shinichirou Miyazaki