Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: A semiconductor device according to an embodiment includes a first contact electrically connected to a first conductive layer with a diameter size smaller than a diameter size of a first support pillar at a region position on an inner side in a radial direction of the first support pillar in a first region and extending to the opposite side of the substrate with respect to the first conductive layer; and a second contact electrically connected to a second conductive layer with a diameter size smaller than a diameter size of a second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer.

Abstract: A semiconductor device according to an embodiment includes a first contact electrically connected to a first conductive layer with a diameter size smaller than a diameter size of a first support pillar at a region position on an inner side in a radial direction of the first support pillar in a first region and extending to the opposite side of the substrate with respect to the first conductive layer; and a second contact electrically connected to a second conductive layer with a diameter size smaller than a diameter size of a second support pillar at a position of penetrating through the first conductive layer at a region position on an inner side in a radial direction of the second support pillar in the first region and extending to the opposite side of the substrate with respect to the second conductive layer.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: According to one embodiment, a semiconductor device includes a base, a memory cell region on the base comprising a first plurality of conductive layers and a second plurality of insulating layers, wherein an insulating layer extends between, and separates, each two adjacent conductive layers of the first plurality of conductive layers. A first stacked body and a second stacked body are located on the base, and includes a plurality of insulating layers and a plurality of conductive layers fewer than the number of first conductive layers, and an insulating layer extends between, and separates, each two adjacent conductive layers of the plurality of conductive layers in each stacked body. The end portions of the stacked bodies include a stair portion having a stair-like shape wherein a surface of each of the conductive layers thereof is exposed.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes first and second connectors, first and second conductive layers, a first insulating region, and a memory portion. The first connector extends in a first direction. The first conductive layer is electrically connected to the first connector, and includes a first planar region, a first overlap region, a first side surface region, and a first crossing side surface region. The second connector extends in the first direction. The second conductive layer is electrically connected to the second connector, and includes a second planar region, a second overlap region, a second side surface region, and a second crossing side surface region. The first insulating region is provided between the first and second conductive layers. The memory portion is connected to the first and second planar regions.

Abstract: A storage medium storing a simulation program according to the present embodiment stores a simulation program for making a simulation device carry out a simulation of the shape of a semiconductor device. In accordance with the program, the simulation device simulates a manufacturing process using first three-dimensional shape data to calculate second three-dimensional shape data. Third three-dimensional shape data is calculated as a difference between the first three-dimensional shape data and the second three-dimensional shape data. Data about a calculation formula for calculating the second three-dimensional shape data from the first three-dimensional shape data by using the third three-dimensional shape data is generated. A data size of data including the data about the calculation formula and the third three-dimensional shape data is compared to a data size of the second three-dimensional shape data, and the data having a smaller data size is stored in the storage.

Abstract: A pattern shape evaluation method includes acquiring an image of an evaluation target pattern including a plurality of element patterns; detecting edge of the evaluation target pattern from the image; classifying the detected edge of the evaluation target pattern into a plurality of evaluation target pattern edge groups; acquiring edge of a reference pattern serving as an evaluation standard for the element patterns; classifying the edge of the reference pattern into a plurality of reference pattern edge groups; selecting a reference pattern edge group to be aligned with the edge of the evaluation target pattern from the classified reference pattern edge groups; aligning the edge of the selected reference pattern edge group with the edge of the evaluation target pattern; and evaluating the shape of the evaluation target pattern by use of the result of the alignment.

Abstract: A pattern shape evaluation method includes acquiring design data accompanied by an evaluation area in which information on a particular evaluation area within a pattern of a semiconductor device is added to the design data for the pattern, acquiring an image of the pattern, generating edge data for the pattern from the image of the pattern, aligning the design data accompanied by the evaluation area with the edge data and evaluating the shape of the pattern within the evaluation area after the alignment.

Abstract: A micropattern measuring method disclosed herein includes acquiring an image of a micropattern including plural layers; extracting a rough outline of the micropattern in the image as a sequence of points including plural points; dividing the plural points composing the sequence of points into groups; making each of the groups as each of patterns belong to any of the plural layers; and acquiring edge coordinates of a pattern to be measured from the patterns which are made to belong to the respective layers.

Abstract: A graphic contour extracting method includes: acquiring an image of a graphic form to be inspected; defining an inspection region for the image of the graphic form to be inspected by an inspection graphic form including at least one of a circle, an ellipse, a rectangle, a first rectangular graphic form, a second rectangular graphic form and a closed curved graphic form, at least one end of the first rectangular graphic form being replaced with any one of a semi-circle, a semi-ellipse and a parabola, at least one of four corners of the second rectangular graphic form being replaced with a ¼ circle or a ¼ ellipse, the closed curved graphic form being expressed by the following expression: ( x - x 0 ) 4 a 4 + ( y - y 0 ) 4 b 4 = 1 , and the inspection graphic form having an edge searching direction previously defined for at least one component thereof; and searching an edge of the graphic form to be inspected on the basis of the inspection graphic form to acquire contour infor

Abstract: A pattern shape evaluation method includes acquiring an image of an evaluation target pattern including a plurality of element patterns; detecting edge of the evaluation target pattern from the image; classifying the detected edge of the evaluation target pattern into a plurality of evaluation target pattern edge groups; acquiring edge of a reference pattern serving as an evaluation standard for the element patterns; classifying the edge of the reference pattern into a plurality of reference pattern edge groups; selecting a reference pattern edge group to be aligned with the edge of the evaluation target pattern from the classified reference pattern edge groups; aligning the edge of the selected reference pattern edge group with the edge of the evaluation target pattern; and evaluating the shape of the evaluation target pattern by use of the result of the alignment.

Abstract: A pattern shape evaluation method includes acquiring design data accompanied by an evaluation area in which information on a particular evaluation area within a pattern of a semiconductor device is added to the design data for the pattern, acquiring an image of the pattern, generating edge data for the pattern from the image of the pattern, aligning the design data accompanied by the evaluation area with the edge data and evaluating the shape of the pattern within the evaluation area after the alignment.

Abstract: A micropattern measuring method disclosed herein comprises acquiring an image of a micropattern including plural layers; extracting a rough outline of the micropattern in the image as a sequence of points including plural points; dividing the plural points composing the sequence of points into groups; making each of the groups as each of patterns belong to any of the plural layers; and acquiring edge coordinates of a pattern to be measured from the patterns which are made to belong to the respective layers.

Abstract: A micropattern measuring method discloses herein includes acquiring an image of a micropattern including plural layers; extracting a rough outline of the micropattern in the image as a sequence of points including plural points; dividing the plural points composing the sequence of points into groups; making each of the groups as each of patterns belong to any of the plural layers; and acquiring edge coordinates of a pattern to be measured from the patterns which are made to belong to the respective layers.